Controlling the W5500 from a RISC-V Softcore: Ethernet Integration on Basys‑3 FPGA
A RISC‑V CPU on an FPGA successfully talks to a W5500 chip via SPI, enabling hardware-based Ethernet with ARP scan detection.
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Components
Hardware componentsRISC-V Internationa - RISC-V RV32I
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United States Department of Defense - VHDL
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Project description
📌 What is This Project? This project is a minimal RISC‑V softcore CPU, implemented in VHDL for the Digilent Basys‑3 FPGA development board. It aims to provide a clear, single-cycle implementation of the RV32I instruction set, making it ideal for learning architecture and hardware-software integration. 🧩 Key Features Single-cycle RISC‑V (RV32I) CPU in VHDL Toolchain to convert compiled ELF → HEX → VHDL ROM initialization Fully synthesizable on Basys‑3 FPGA Supports bare-metal RISC‑V C/Assembly programs 🎯 Educational Focus Learn instruction-level CPU design Explore memory-mapped I/O…
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