Vivado FPGA Learning Projects with SPI, UART, VGA, MicroBlaze, and W5500-Oriented Integration
A Vivado FPGA practice repository covering HDL basics, FSMs, SPI/UART/VGA interfaces, memory/IP blocks, and MicroBlaze-based AXI systems.
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Project description
Project Overview vivado_pj is a collection of FPGA practice projects built around AMD/Xilinx Vivado. Rather than being a single finished product, it is best understood as a learning-oriented repository that gathers multiple Vivado project examples across digital logic, peripheral control, IP usage, and soft-processor-based system design. The repository contains many folders that reflect a step-by-step FPGA learning path: basic logic blocks, registers, counters, clock dividers, FSM examples, SPI, UART, VGA, SRAM-related work, AXI Stream, memory IP, MicroBlaze projects, and a W5500-oriented…
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