UCC

This article details MicroPython performance optimizations such as memory tuning, native/viper compilation, mpy-cross and RP2040 hardware optimizations.

This article introduces MicroPython system architecture, startup workflow, GC, REPL, and core modules including machine and rp2 for RP2040.

ControllersTech's Part 6 tutorial builds a dynamic CGI web server on STM32F103 with W5500 hardware sockets: LED control, PWM slider, and live BME280 JSON data.

MeshCam is an ESP32-based wildlife camera network that transfers motion-triggered images

An ESP32-S3 and W5500-based learning platform that simulates industrial Modbus TCP devices and supports Ethernet OTA, configurable network settings, an HTTP API

An industrial LoRa-to-Ethernet gateway that combines an ESP32-S3 control board, W5500 wired networking, PoE, isolated digital I/O, and an SX1262 LoRa DTU.

Third-Party Hardware Drivers are GSDK Extension to provide support for third-party external hardware.

MicroROS-Pub

esphome-p1

used by numerous heating systems).

The xfrpc project is an implementation of frp client written in C language for OpenWRT and IOT system. The main motivation of this project is to provide a light

This article illustrates the merits of MicroPython, its source structure, code execution flow and multiple supported hardware ports.

This article covers MicroPython’s development timeline, introduces PyMite, and compares the differences between MicroPython and its derivative CircuitPython.

This article introduces MicroPython, its distinctions from CPython, supported hardware platforms, .mpy precompiled bytecode, and the main differences in syntax,

This article introduces RP2040 Sysinfo identification registers, Syscfg system configuration registers and the simulation-only TBMan module.

This article introduces RP2040 GPIO pins, pin multiplexing function selection, external interrupts and configurable electrical parameters of IO pads.

This article explains RP2040’s clock tree system, covering multiple clock sources, frequency configuration, independent gating and power-saving principles.

This article introduces RP2040's power-on finite-state machine, its hardware sequential startup flow and controlled modules during chip power-up.

This article explains two reset types of RP2040: full chip reset and independent subsystem peripheral reset, along with relevant reset signals.

Cyclone V FPGA에 구현한 2채널 디지털 락인 증폭기. 잡음 속 미약 신호의 크기·위상차를 실시간 측정해 W5500 TCP로 호스트 PC에 스트리밍합니다.

This article introduces RP2040 low-power strategies to cut dynamic and static power, including clock gating, clock switching and DORMANT deep sleep mode.

This article covers RP2040's on-chip core regulator, its adjustable voltage range, three operation modes, ROK indicator and configuration registers.

This article introduces RP2040's multi-rail power supply system and several practical power supply wiring schemes.

This article introduces RP2040’s power-on boot sequence, covering hardware initialization and BootROM-driven Flash/USB boot modes.