FPGA fast deployment of Ethernet

Question

With the rapid development of embedded system industry, IC is moving toward highly integrated and low-cost. ARM microcontroller has gradually eroding the traditional 8/16/32 bit microcontroller market for recent years by its powerful resources, flexible development environment and the low prices. At the same time, the cost of FPGA also greatly reduced from high level. And with its high integrated, high performance, low power consumption, and open development environment made FPGA divided the embedded system market together with ARM. Many people are not familiar with FPGA. For peoples accustomed to using the software on a single chip low level programming language, FPGA is somewhat difficult or incomprehensible. FPGA is taken from the first letter of Field Programmable Gate Array. Literally we can see, FPGA is actually a collection of numerous gates, but is different to our traditional logic, FPGA supports user-to-door to recompile the circuit. An analogy:for microcontroller programming, it likes usingfixedblock to build products. But for FPGA, it is to build from nothing to start, first put the building blocks we need to produce a good customizedmodeling, and then used to build the product. This means that many protocols and functions in the FPGA need our own engineers build independently. For PC users, the platform TCP/IPprotocol is piece of cake. For single-chip platform users, thin TCP/IPstacks also become very common, but for FPGA users, re- build a TCP/IP protocol, it is no doubt to be aheadache. WIZnet hardware and TCP/IP protocol stacks designed for FPGA users with one of the most efficient and fast deployment for Ethernet connectivity. FPGA users firstly configure the special registersof the hardware TCP/IPchip, and thendump the data to the address like operating RAM. FPGA engineers should be familiarized with the operation of external RAM. Of course, to getbest performance for FPGA users, we recommend the use of this high-speed Ethernet W5300 chip with 128K RAMinside, supports 8/16 bit BUS communication and DMA, actual throughput can be up to 80Mbps. Hardware connection W5300 has 8-bitand 16-bit two type of communication method;for higher communication speed, we usuallychoose 16 bitfor communication. So, no need to use address A0 ,just use A1 through A9 as an address line. Software Design W5300 software project as below: Firstcompiling the registers preparation part, the file w5300timing achieves W5300 register file read and write timing control, according to the W5300 literacy and FPGA clock cycle timing requirements for the register read, write or delay for controlling. Secondly, initializing the W5300, the w5300_init file for the initialization process of W5300, calling this moduleto perform soft reset, configure MAC address, IP address, gateway , subnet mask, buffer configuration; After finishing the initialization of W5300, computer PINGprogram can be used to test the connection with the device, the remaining files can be prepared…

vport · Answer

I am unable to find source code where to find