W5500 SPI Bottleneck

Question

Hi! I am aware that in using the W5500, the SPI is the major cause of bottleneck. When doing IPerf using atmega328p chip on W5500. The SPI we use is about 8MHz. Now, we are expecting the results to be at least near 8Mbps with a few losses on start/stop events. But what we are getting is just ~3 Mbps. Reading through the results of those who had done this activity, our results are comparable. But I can’t explain why this is happening and I can’t find anything. Hoping someone can explain this to us.

irina · Answer

it needs 8 clock for 1-byte send. W5500 SPI Frame consists of 16bits Offset Address in Address Phase, 8bits Control Phase and N bytes Data Phase. it needs at least 32 clock for a valid data. Also, Network speed and SPI clock speed is different. I think if network speed is 3Mbps, it is fast thanks, best regards,

Philipp K · Answer

I can’t really tell with 100% certainity, but in the case of an atmega328 it may depend on the way the SPI works. Note that, for instance, these chips don’t have DMA (afaik), so after every transfer the controller needs to stop what it is doing, read the received byte and copy it to the appropriate location in memory, check the transfer state and initiate the next transfer. I suppose this wouldn’t matter when manipulating registers, but during burst transfers this may take up some time. Now, I can’t guarantee that this is the acutal reason, but this would be my assumption as to why this is the result that you get.