Foot print pattern foer W5500

Question

Please send me recommended Foot print pattern or Gabor data of ref circuit for W5500? Or please send me application note for PCB Lay out? Because customer proto type of power consumption is bigger (3.3V VDD and VDDA. Please let me know the MAX value of Power Dissipation on page 62 5.4? Please let me know the ripple noise limitation for VDDA and VDD at 100Hz to 800KHz Frequency. E.g. Id exceed 100mVp-p , the communication quality become Bad. Please let me know power ON and Off Spec. E.g. Power ON stage VDD and VDDA must apply over 90% in 10msec . If exceed 10msec, this cause communication error or not. Best Regards

Eugeny · Answer

hiroshiiwasaki: Please send me recommended Foot print pattern or Gabor data of ref circuit for W5500? Datasheet says 48 Pin LQFP Lead-Free Package (7x7mm, 0.5mm pitch) and you take respective package drawing for your EDA tool you use. For example, I am sure EAGLE is having one in standard ref-packages library, the only thing you need to check is that pad sizes are compliant to the W5500 datasheet chip drawing. hiroshiiwasaki: Or please send me application note for PCB Lay out? This archive contains document on PCB design guidelines for W5100, must be also applicable to W5500. hiroshiiwasaki: Please let me know the MAX value of Power Dissipation on page 62 5.4? There’re several reference circuit diagrams atvailable here. I assume that “typical” value applies to the “typical” implementation, thus power consumption of the W5500 and related circuits should be close to the declared. If you are going to change the circuit, you will need to make respective corrections. I think you should be safe if selecting 1A PWM supply device (or converter from another, higher voltage). hiroshiiwasaki: E.g. Id exceed 100mVp-p , the communication quality become Bad. Datasheet says 2.96 to 3.63 V, formally it is voltage level chip operation is guaranteed by the manufacturer. Said that, you must design your board, including supply circuits, to ensure there’s enough power current at 3.3 V level, and noise is minimized by the passive decoupling mechanisms (e.g. capacitors) and active decoupling mechanisms (e.g. DC-DC converter). hiroshiiwasaki: E.g. Power ON stage VDD and VDDA must apply over 90% in 10msec I never seen such info for WIZnet products. I can say that power must be within declared operating level for some time (see reset specification of the datasheet) for PLL to lock, then your circuit uses hardware reset to reset the W5500, and then it is expected to operate normally and you can proceed with its configuration for networking.