W7500 flash memory interface registers

Question

Hi, Section 9.2.1 in the W7500 manual describes the addresses of the flash registers, but there are no details on the bit arrangement in FACCR, FACTRLR and FSTATR. Would it be possible to get this information?

lawrence · Answer

Hello, aon After Table 6, there is all description of using Flash memory Interface register with unlock FACCR, read operation, flash erase and program operation. I hope you can fine how to handle them. If there is no what you look for, please let me know . Thank you Lawrence

aon · Answer

Yes, I’ve found the descriptions. But for example, in section 9.2.2 on page 87 of the reference manual: Check that no main Flash memory operation is ongoing by checking the RDY bit in the FSTATR register. … Set FEN and CTRL bits in the FACCR register. I can’t find a table anywhere that tells me which bit is RDY in FSTATR, and which bits are FEN and CTRL in FACCR? And so on.

aon · Answer

Hi, Any news on this? Thanks.

lawrence · Answer

Hello, aon Thank you for your interest. I review the flash control and I realized that I supposed to say to you at first… We support IAP to erase and write flash but it is not possible to control flash without IAP. I think datasheet made you confused with chapter 9… so sorry about that… We have an IAP example here [url]https://github.com/Wiznet/W7500[/url] please refer it and ask any thing about it! Thank you lawrence

lawrence · Answer

Please refer how to use IAP function [url]http://wizwiki.net/wiki/doku.php?id=products:w7500:peripherals:flash[/url] Thank you lawrence

aon · Answer

OK, thank you Lawrence.

Hooligan0 · Answer

Hi lawrence, lawrence: http://wizwiki.net/wiki/doku.php?id=products:w7500:peripherals:flash I think there are two errors into the table (on web and into datasheet). Each memory block is 4k but the table show 4 sectors of 256 bytes for each block … If the first sector number is “0” … then the last must be 31 (not 32)

lawrence · Answer

Hello, Hooligan0 Thank you so much for finding the incorrect part of the datasheet We will make sure the flash memory. And… I am very sorry to make you so confused with the table… Each block has 4KB and 16 Sectors. (but I know the table only show 4 Sectors…) Then as you said, 0 ~ 31 block and 0 ~ 511 sectors is right! ( datasheet is wrong) As soon as possible, we will modify the errors in flash memory description. Thank you again! lawrence

lawrence · Answer

Hello, before datasheet corrected, please refer wizwiki page [url]http://wizwiki.net/wiki/doku.php?id=products:w7500:peripherals:flash[/url] Thank you lawrence

Hooligan0 · Answer

[quote=“aon”]Hi, Section 9.2.1 in the W7500 manual describes the addresses of the flash registers, but there are no details on the bit arrangement in FACCR, FACTRLR and FSTATR. Would it be possible to get this information?[/quote] FEN and CTRL bits of FACCR are located at bits 16 and 17 (write 0x00030000 to set) SER of FACTRLR seems to be at bit 27 (0x08000000) For the RDY bit, wait until FSTATR is 0x00

Hooligan0 · Answer

Blocks DATA0 and DATA1 There is no technical restrictions (as i know) about DATA0 and DATA1. You can use this pages for custom datas like configs, keys, … You can use other flash pages for same purpose but using DATAx pages reduce risk of erasing/modifying firmware (and use a better protecting strategy) Where did you see “0x1FFF1001 & 0x010” (i have not the whole docs and code in mind) About Thumb code The W7500 chip contains an ARM cortex M0 cpu. This processor use by default 32 bits instructions set but may also support 16 bits instruction set called Thumb instructions. This reduce code size and improve performance in many cases. See chap A5 of v7-M doc https://static.docs.arm.com/ddi0403/e/DDI0403E_B_armv7m_arm.pdf

SURYA OBULA REDDY NA · Answer

#define IAP_ENTRY (0x1FFF1001) // Because Thum code #define IAP_ERAS (0x010) It will be appeared to you in Flash W7500x_peripheral Example Code… github.com Wiznet/W7500P/blob/master/W7500P_FW/Projects/Peripheral_Examples/Flash/IAP_Example/main.c /******************************************************************************************************************************************************* * Copyright �� 2016 <WIZnet Co.,Ltd.> * Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the ��Software��), * to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. * THE SOFTWARE IS PROVIDED ��AS IS��, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. *********************************************************************************************************************************************************/ /** ****************************************************************************** * @file Flash/IAP_Example/main.c * @author IOP Team * @version V1.0.0 * @date 26-AUG-2015 * @brief Main program body This file has been truncated. show original

Hooligan0 · Answer

Oh, i have badly understand your first question (i have read “&” as logic operator, not just as “and” ) The first value (0x1FFF1001) is the address of a small piece of code located into a reserved memory. This piece of code contains functions that can be used to update flash content (IAP). I don’t know if this is a ROM or a reserved flash page because the doc about this page is poor (this is not important if you just want to use it). When you call this IAP code, you need to give arguments. One of them is a code that define the command you want to call (erase, write, …). The second value of your question (0x10) is one of this commands.

SURYA OBULA REDDY NA · Answer

Hi Hooligan, I have a problem with the UART Configuration in Example Code In that examples for Uart0 and Uart1 gpio’s are not configured in Polling UART Example

Hooligan0 · Answer

Please, do not reuse a topic for another question I will reply after your other post : UART0 and UART1 Gpio's in Polling UART Example W7500x UART0 and UART1 Gpio’s are not configured in Polling UART Example Code…

Ilya · Answer

Hello! How can I learn a number of the bit of SER in the register FCTRLR, and also a number of the bits of SZ in the register FACCR and a number of the bits of WR and WRI in the register FCTRLR???

Ilya · Answer

Hello, Hooligan! Thank you!