concurrent-data-capture

Project description

The module's inputs and outputs are as follows: clk: clock signal miso: Master In Slave Out (MISO) pin instruction_input_valid: Signal indicating the validity of the instruction input instruction_input: the input instruction data_input_valid: signal indicating the validity of the data input data_input: input data flush_requested: signal requesting to flush data to the TX buffer mosi: Master Out Slave In (MOSI) pin spi_clk: SPI clock spi_chip_select_n: SPI chip select signal data_read: read data (UDP response, etc.) data_read_valid: signal indicating the validity of the read data…