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quasiSoC (RISCV)

quasiSoC (RISCV) peri driver

lawrence

Published May 30, 2023

145 UCC

9 WCC

19 VAR

Original author: regymmOriginal source (new tab)

quasiSoC (RISCV)

Project description

Quasi SoC

Crappy RISC-V CPU and fancy peripherals designed to be useful. No-MMU Linux capable. Free-software toolchain ready. Prioritize compatibility and easy-to-understand -- if I can write this, you also can.

quasiSoC (RISCV), Quasi SoC

 

Peripherals

  •  AXI MIG DDR2/DDR3
  • ESP-PSRAM64H (8 MB) QPI mode @ 62.5 M, burst R/W
  • SDRAM
  • GPIO (LEDs, buttons, switches)
  • UART (115200/921600/1843200 baud), boot from UART, rest from UART
  • SD card (SPI mode, SDHC)
  • PS/2 keyboard
  • PS/2 mouse
  • Graphics
    • HDMI, character terminal, frame buffer graphics(320x240 8-bit color, 640x480 2-bit monochrome)
      • Quality of life fixes
    • Old good VGA
    • ILI9486 480x320 LCD
      • Refresh rate upgrade
  • CH375 USB disk
  • W5500 ethernet module
    • W5500 as MAC with LwIP stack
  • Bus arbitration: Multiple hosts, "DMA"
  • Bus converter: Use AXI peripherals
  • Hart transplant: Use other RISC-V cores with my peripherals
  • Xeno transplant: Use ARM or x86 cores with my peripherals

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