RiskZero FPGA Workstation Single Board Computer
The aim of this project is to provide an FPGA implementation of the Phasor Estimation algorithm in this paper: https://ieeexplore.ieee.org/d
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Project description
https://riskfive.com/RiskProject_overview.htm
- One Spartan-6 FPGA XC6SLX9-TQ144 serving as a reconfigurable CPU.
- 4 megabytes of Zero Bus Turnaround (ZBT) memory.
- Two SD cards (one micro and one full size).
- HDMI video output.
- Two FPGA boot flash chips whose roles can be swapped with a switch.
- PS2 connectors for the keyboard and mouse.
- Three PMOD connectors for SPI-based data acquisition. See Note 1.
- USB-to-UART and USB-to-JTAG converter chip FT2232H.
- SPI-to-Ethernet converter W5500 with the on-chip TCP/IP stack.
- A socket for the 2.4 GHz Nordic Semi NRF24L01 wireless module.
- A socket for the 2.4 GHz Sparkfun WiFi WRL-13678 wireless module. NEW on
same site(another project) : https://oldmaker.wiznet.io/2022/06/01/riskfive-fpga-development-board-2/
