[From QnA]WIZ810JM module timing

Question

I wish to connect the WIZ810JM module with a Z80, but I have some doubts: Q1) The Z80 asserts the MREQ, then stabilizes the data bus, and then it asserts the WR line. The time from the falling of MREQ (CS) to the falling of WR is 250ns for a 4MHz clock. Will it work with W5100? The data sheet says that the maximum time from CW to WR is 1ns but this number seems too strict. Q2) Due to the delays in glue logic chips I am using, for a reading operation, the RD line goes down, then after 15ns the CS goes down, then I spent 375ns with both lines down. At the end, the RD line goes up, then after 15ns the CS goes up. Will it work with M5100?? Q3) Considering that I will need to register the WR, CS and RD lines, will the 5100 operate with simultaneous activation of these signals? Q4) A generic question that may answer the previous ones: Are the Read/Write operations of the W5100 controlled by BOTH CS and RD (or WR), as in a SRAM chip, or is it really necessary that the CS line goes down first, and goes up last (with the RD/WR happening within 1ns from CS)? Best regards,

wiznetmuseum · Answer

Dear Sir, Max 1ns is the time to guarantee /WR goes down after /CS down in the view of W5100. So, in the view of device, it can be more 1ns for /WR to go down after /CS down. Even it is 0ns, it does not matter As answered to Q1, in the view of device, it can be more than 1ns. W5100 operates as like general SRAM. /CS, RD, /WR can be controlled simultaneously. 1ns described in datasheet is the value to prevent the negative. regards,

GilesGoat · Answer

Hi guys, first time logger here, found this place yesterday precisely while trying to understand better the WIZ datasheet. I am not sure if it’s just me or what but in fact I found the timings descriptions lightly confusing as well and me too I just bought one of those modules to attach it to a Z80 CPU. Let’s take for example your WIZ datasheet section 3.3 “Register/Memory WRITE timing” the way it LOOKS like from what you write is that it’s “imperative” that /WR MUST go to ‘0’ NO LONGER than 1ns after WR /CS, which as the other guy says it’s a very strict requirement. What you say in the reply instead seems to say like "no actually, it means that before the WIZ realizes that /WR is ‘0’ after /CS is ‘0’ is about 1 ns and if I read your reply above correctly seems in fact to say "even if they go down simultaneously it does not matter the WIZ will take no longer than 1ns to understand that /WR is actually ‘0’ ". At this point I am not sure “what I would have written in the datasheet” maybe I would have said “/CS low to /WR understood as low” MAX 1ns … I suppose at this point that “parameter 5” that you call “/WR high to /CS high time” means “it takes max 1ns for the WIZ to understand that /WR is returned back to ‘1’ once you change it”. Likewise “parameter 6” “/WR low to valid data time MX 14 ns” I suppose then means “it takes MAX 14 ns since /WR goes ‘0’ before the WIZ accepts it as valid data”, however again as somewhere else you specify the data is latched on the raising edge of /WR I guess that time could be even longer. What actually it’s not specified by I suppose at this point “probably is MAX 1ns” is if a “data retention time” is needed after /WR goes ‘1’ to latch it. Your answer to 3/4 to me is still lightly confusing, are you saying basically that “/WR or /RD can go down/up even simultaneously with /CS OR within the time /CS is ‘0’ but NOT BEFORE” ? In other words a scenario like : ^ = '1', _ = '0' /CS : ^^^^^^^^^^_________________^^^^^^^^^^^^^ /WR…

bongbong · Answer

Hi guys, refer to my comments. in herosmirr’s 2nd posting, [i]Dear Sir, Max 1ns is the time to guarantee /WR goes down after /CS down in the view of W5100. So, in the view of device, it can be more 1ns for /WR to go down after /CS down. Even it is 0ns, it does not matter As answered to Q1, in the view of device, it can be more than 1ns. [/i] [quote] [color=#800000]YES, in the view of device, it can be more than 1ns. That is, For example IF CS goes to low and wait 50ns(or more than), WR/RD goes to low, then there is no problem. as following timing is very good.[/color] [code]^ = ‘1’, _ = ‘0’ /CS : ^^^^_______________________________^^^^^ /RD or /WR : ^^^^^^^^^^_________________^^^^^^^^^^^^[1][/quote] 3) 4) W5100 operates as like general SRAM. /CS, RD, /WR can be controlled simultaneously. 1ns described in datasheet is the value to prevent the negative. [color=#800000]YES, 1ns, this value represents to prevent the negative[/color]. PS. I agree to make confusion used in “1ns” in datasheet. I try to discuss this issue with the WIZnet engineers and make a better solution to represent timing ASAP. Best Regards, /code ↩︎

GilesGoat · Answer

Hi, thanks for the reply … I tell you what “soon” ( time permitting ) I’ll try to attach the module to that Z80 thing and I think “a bit of testing will be the best thing to see if it works”. I am inclined to think that if it’s like an SRAM then simply ( in the case of a Z80 ) routing /MREQ + address decoding into /CS and routing /RD /WR into the same lines should work. The way Z80 works it always asserts /MREQ before ( about 10 ns before regardless of clock speed ) /RD or /WR but puts all of them back to “inactive” ( 1 ) simultaneously. In my case I have a little difference to test as I intentionally delayed /MREQ 1/2 clock cycle to give the ram more time to get the address on the bus, this would make in the READ case have the /RD signal going ‘0’ before your /CS but I believe it’s still going to work, WRITE case would still be “/CS first and /WR after”. When I’ll make it work I may post a little schematics/explanations on this forum so we can say “ok look, this way it works” I’ll keep you posted.