MR_ALIGN and RX_FIFOR Problem

Question

I have the following problem. In direct mode reset mr_align to zero during initialization, open TCP socket and send 12 bytes from PC to W5300. I read RSR register and as I expected it has value 14 for a long period of time, but after some time I read value 12. In this case my communication crush, because I read from RX_FIFOR not a length of data packet, I read data and things that it is data lengths so after that I can read greater quantity of words that W5300 has in FIFO buffer. I do not understand what happens. May be someone can help me? In normal situation when I read value 14 I read data length from RX_FIFOR after that I read all data from RX_FIFOR, chech the RSR register again it has 0 value and confirms with RECV command.

alenic · Answer

Hi, I use 16 bit data bus mode. Code in the attachment. W5300_1.c (4.59 KB) W5300_1.h (7.76 KB) Socket_1.c (7.04 KB)

alenic · Answer

In the above attachment I set align bit, because I take a code from working project. For this moment it is my solution of my problem.

alenic · Answer

I wonder when and how do you call W5300_recv(). I use RTOS (with name RTOS). W5300_recv() is a blocking function. I call it from communication task. Like this: while(TRUE) { if((ErororCode = W5300_OpenSocket(Socket0, Sn_MR_TCP, Port)) == 0) ErororCode = W5300_Listen(Socket0, 0L); while(ErororCode == 0) { len = 1024; // Waite here while received data or timeout if((ErororCode = W5300_recv(Socket0, Inbuf, &len, 2000L)) == 0) { if(len == 0) continue; // process data ErororCode = W5300_send(Socket0, DataBuf, len, 1000L); // send a answer RTX_Sleep_Time(2); // sleep a little } } W5300_CloseSocket(Socket0); }

alenic · Answer

Why you read Sn_MR every Sn_RX_FIFOR read? I read in datasheet: [quote]If the host system uses 8 bit data bus width, Sn_RX_FIFOR0 and Sn_RX_FIFOR1 should be accessed in a pair as like Sn_TX_FIFOR. It is not allowed to access Sn_RX_FIFOR0 and Sn_RX_FIFOR1 right after accessing Sn_TX_FIFOR0 and Sn_TX_FIFOR1. These are cause for the incorrect read. In order to prevent this, after reading Sn_TX_FIFOR0 and Sn_TX_FIFOR1, the host reads any register such as Sn_MR and then access Sn_RX_FIFOR.[/quote] When I found my problem I thought may be the same rule working in 16 bit mode. In interrupt I just count the quantity of data packets (or interrupts request). All manipulations with data I make in W5300_recv(). May be, while I process data from one data packet another one will be received so at the end of W5300_recv() I check how many packet in W5300 data buffer and if there is no data packets I switch of the message in this case function W5300_recv() will be blocked in next call while new data comes. I work with Modbus/TCP protocol and another PC waits an answer before send a new one request so In most cases my communication looks like: request → answer ->request - > answer->…

alenic · Answer

Hi, How about testing my recommended code? I do not have equipment at this moment. I will test it after one or two weeks, when new equipment will arrive. I wonder what is caused by wrong RSR? explain more detail your phenomenon? So, I have test schema one PC and board with W5300 and connections between them. On PC side I use modbus pool to generates a requests. PC send a request (12 byte) and waits an answer if there is no answer for 1seconds connections closed. If answer returned from my board PC prints the data and send new request. Delay between request in this case will be 100 ms. On my board I have an ability to print some data via telnet (I use com port RS 232). Here I print rsr register each time I received the data. Usually here 14 byte length 12 modbus header + 2 byte packet info. But some times I read from rsr register 12. In this case I try to print FIFO data and see just modbus header without packet info. In this case I read transaction ID instead packet length and try to read more data that W5300 has in buffer.

alenic · Answer

Hi, Ok, I will check this moment. But as I told after new equipment will come. I will write a result here. Thank You for help!

alenic · Answer

Hi, I solved my problem. I just included reading of RX_FIFO register into critical section. Thank You.