wiz830MJ stops working after some time

Question

Hi, I’ve been working with wiz830MJ module for several days, I’ve managed to run TCP Server mode successfully (module received data from PC Client and sent data to it). After several days of using module can’t establish a connection! Socket is initialized, but ping command isn’t carried out, PC client can’t connect. Socket closes very often (at listen stage or at establishment stage: Sn_SSR=0x00).

Sergey · Answer

It seems there was no contact in my self-made cable… )

jbkim · Answer

Sometimes small thing make problem. Anyway it’s good to hear that you find the cause of the problem.

Sergey · Answer

But I’ve faced another problem: module doesn’t work every time when I start host processor programme (I use Altera’s Nios2). Sometimes it works, sometimes it doesn’t. Simple modification of the programme (for example, adding of 1 printf(regN_value) operator - for debugging purpose) could lead to fail. Then I can make 1 more modification and module works OK. Sometimes module gets to “socket listen” mode, but ping command doesn’t work and printf(IP_reg) shows 0!!! It seems that in that case IP address isn’t written correctly. In another situation module doesn’t go into SOCKET_LISTEN mode. But sometimes everything works right: I achieved data speed more than 20 Mbits/s in each direction. I’ve checked address bus, data bus, СS, WR, RD, but haven’t seen any problem with them.

jbkim · Answer

Do you have working module and have a problem with specific module?

Sergey · Answer

I’ve got two modules, both of them work the way I posted above. I guess, at least one problem could be with writing process (from time to time IP register doesn’t contain right IP address). In my system data appear on the tristate bus before wr and cs signals go low (Altera’s tristate controller works this way). Is it correct or not? Does datasheet mean that data must be on the bus no earlier than tDATAs?

Sergey · Answer

As regard to write timing, WR and CS goes low at the same moment, WR stays low for 70 ns, CS stays low for 90 ns. WDF[2…0]=0, so data sample is taken 7 ns later from the moment when wr/cs are deasserted. Also I’ve tried WDF=3 but didn’t see any difference.

jbkim · Answer

Can you check the timing with oscilloscope? If yes, it’ll be helpful for us to resolve the problem.

Sergey · Answer

Yes, I’ve checked timings, they look OK.

jbkim · Answer

Please send the timing to us then we’ll check it.

Sergey · Answer

We are having Christmas holidays till 9th of January, so I’m not at work now. I’ll send timings later. How to do it? Is there a tool for that on this site?

jbkim · Answer

You can attached the picture of timing. There is “upload attachment” tab under the edit area.

Sergey · Answer

Hi, I attached a .jpg file with read/write diagram. D7,D6-addr1,addr0, D4,D3-data1,data0, D2-RD, D1-WR, D0-CS. I use following code to get this diagram: IOWR(W5300,0x001c,0x0001); while(1) {IOWR(W5300,0x0201,0xff02); IORD(W5300,0x001c);} IOWR: 2nd parameter -address, 3rd parameter - data; IORD: 2nd parameter - address.

Sergey · Answer

The problem is still actual)

Sergey · Answer

Code I posted above was used just to get write/read diagram, it’s not a part of a programme. I checked write/read operations (IDR, GAR), there wasn’t problem with them. It seems that issue is related to processor (sometimes adding of 1 printf operator leads to fail - no ping). I also worked with wiz820io (the system was the same - Wiz module+ FPGA based Nios 2 host processor), but didn’t have such an issue. If I manage to find the reason I’ll post an explanation here.