W5500 latency from Receive/Send done to Interrupt issued

Question

【English/英文】 Hi, we are trying to implement a network time and frequency transfer system using Wiznet's W5500 chips. In order to minimize the offset or systematic error of time we had better deal with the latency introduced by the chip itself, while we are lack of equipment that allow us to measure and calibrate it precisely/accurately. Or to be more specific, we are using MACRAW mode and have enabled the interruption function of W5500, seeking 2 pairs of data which are not present among any datasheet/specification or documentation/example we've found: 1、Latency and Jitter between when an Ethernet package's end of Start of Frame Delimiter(SFD) or end of Frame Check Sequence (FCS) pass through the physical layer and when the Interrupt PIN (INTn) asserts to low due to W5500 acknowledging that it has received something from the network.(RECV Interrupt) 2、Same as 1、, but SENDOK Interrupt. We'll appreciate a lot if these data could be provided. 【汉文/Chinese】 你好，我们正尝试用Wiznet W5500芯片构建网络时频传递系统。我们需要处理它自身的延迟来减少时间偏差，但缺少精准测量校准的设备。 具体而言我们正用MACRAW模式并开启了中断，希望得到未在文档或例程里出现的2对数据： 1、从以太网包帧分隔符结尾或帧校验字段结尾流经物理层到W5500因报告从网络上接到数据而拉低中断引脚的延迟和抖动。（接收中断） 2、同1、，但是发送中断 若有提供，感激不尽。

Hannah · Answer

Hello, sorry for the late reply. We are currently reviewing your inquiry, and I will provide you with an update once the review is complete.