No valid signal from MISO

Question

Hello, I am trying to to use a WIZ820io with a w5200 from a custom device, where I have generated the following lines for nSS, SCLK and MOSI: 20190319_1345552851×2138 2.12 MB 20190319_1346134032×3024 3.52 MB Signals from top to bottom: SS, SCLK, MOSI, MISO In this case, I am trying to read the SIPR register (0x000F - 0x0012). Therefore, I am sending 4 bytes (2 for address and 2 for OP=0 and length) Here, checking on the official w5200.h library from github, I can see that length is used to specify how many bytes I want to read. Therefore, in the case of the SIPR register I want to read 4 bytes. Is that correct? What is the difference between nSS and nSCS? In the user manual states nSS for the pinout and nSCS for the SPI signals diagram. They refer to the same pin, right? I have seen in this thread that nSS is driven to 0 and 1 on every byte rather than having it to 0 and sending all the bytes as shown in the datasheet. Thanky for the help. EDIT 1: Here is a better image: Screenshot%20from%202019-03-21%2020-11-111183×155 8.18 KB EDIT 2: I adapted the signals so they match the exact same way as the cited thread: 20190325_1403324032×3024 3.28 MB But still no signal coming back from MISO.

Philipp K · Answer

aripod: What is the difference between nSS and nSCS? In the user manual states nSS for the pinout and nSCS for the SPI signals diagram. They refer to the same pin, right? There shouldn’t be any (if I am not mistaken): SS = Slave Select CS = Chip Select n = Active Low, i. e. 0 means the function is enable/the chip is selected aripod: This waveform looks a bit strange to me, kinda as if two devices are driving the same line; I’ve observed this with I²C devices, where this behavior is desired. It looks like one device is driving the line low, and then a second one joins in. Could you maybe verify that all your host mcu’s gpio pins are correctly configured (especially that MISO is in high impedance/input mode) and that there isn’t any undesired physical connection between IO lines on your board? aripod: I have seen in this thread that nSS is driven to 0 and 1 on every byte rather than having it to 0 and sending all the bytes as shown in the datasheet. I am not sure about the W5200, but the W5500 has two data transfer modes which can be selected individually with each transfert. Either 1, 2 or 4 byte fixed size transfer or a variable data length mode, where the beginning and the end of a frame is marked by the Chip Select going low at the start and high in the end. Toggling CS (or SS for that matter) during a conversation would be very uncommon (and also isn’t done in the manual). I am just not sure what they mean by “The MISO pin should be selected by driving MISO low after the falling edge of the CSn.”. aripod: Therefore, I am sending 4 bytes (2 for address and 2 for OP=0 and length) Do you also send the dummy bytes to give the chip the possibility to transfer the requested data? Or do you only send the 4 instruction bytes? (Looks a bit like it on first glance)

Philipp K · Answer

That’s the CLK pulses that you described, I overlooked that when I looked at your screenshots. So that should be good, too

aripod · Answer

Yes, that is what I meant by sending 5 packets of 8 clock pulses on SCLK. I am sending 4 bytes for address, OP and length and then I have one more byte (because I have length=1) then (with 0x00 rather than 0xFF) that the device should send back data. 4f580e6542d08b7274afac73ccb5c2e5e4da062d2851×2138 3.37 MB

irina · Answer

Hi~aripod The value of SIPR register is empty after reset operation or Initial version. Therefore the value of SIPR register may not be. I recommend reading W5200 version register(0x001F). If you read version register(0x001F), you see the 0x03 through MISO. thanks, BR irina

Philipp K · Answer

aripod: 4f580e6542d08b7274afac73ccb5c2e5e4da062d.jpeg2851×2138 3.37 MB The MOSI waveform looks good to me. nCS going high after every byte is still strange, since as you said, the manual doesn’t mention that, but states explicitly that nCS has to go low before the transmission and high afterwards (no word of in between). I can’t tell for sure, but I’d expect that the chip would understand this as an aborted transmission (though again, this is just a guess). After initialisation, the register should read 0x00, which is what you receive here, but in your first picture without toggling nCS during transfer, you get 0xFF I can see it correctly. Maybe we can get a closeup of that transmission, too, to see what happens there? Otherwise I too would be curious if reading the version register works, as Irina suggested. Also, is the level on the Reset line as expected? (Just a thought)

aripod · Answer

@irina_kim and @Philipp_K, I tested reading the 0x001F register and I got the expected value 0x03: Screenshot%20from%202019-03-26%2009-05-151709×120 6.98 KB The question now is, should I keep it like that, toggling SS with every byte or keep it low until the last byte is transmitted like the manual shows? Screenshot%20from%202019-03-26%2009-07-00744×373 139 KB Thank you both for your help.

Philipp K · Answer

aripod: The question now is, should I keep it like that, toggling SS with every byte or keep it low until the last byte is transmitted like the manual shows? If both ways work for you, I would recommend doing it as described in the manual since I’d say that this is more logical from the interface point of view

Philipp K · Answer

This is really odd. What strikes me is that in this aripod: Screenshot%20from%202019-03-26%2016-15-48962×101 4.44 KB Screenshot from 2019-03-26 16-15-48.png962× Screenshot, MISO is already low before the transmission starts, but in your other example, it was high until the chip started to reply

aripod · Answer

That is actually a very good point. In fact, if we check the screenshots from the other post, we can see that MISO is low.

aripod · Answer

The problem was that it nRESET was low…now it is fixed: Screenshot%20from%202019-03-26%2019-17-011563×136 6.87 KB But still it is still the open question whether MISO should be high or low when it is not transmitting.

irina · Answer

hi~ aripod 962×101 4.44 KB https://forum.wiznet.io/uploads/short-url/tKcruqX5LvJ0luMEuSFgyxpm7gE.png What’s the difference between the above two picture? I think the difference between the above two picture is the initial value of MISO. I can’t confirm the MISO about Version register in first picture. But I can confirm the MISO value about Version register in second picture. It is correct as MISO value. MISO value saw the 0x03. thanks BR irina

aripod · Answer

The issue with the first one, where MISO is always low is because nRESET was also low. In the second one, MISO is 0x03 as expected but the question is if it is ok for MISO to be always high, comparing to the example cited on here where it is low.

Philipp K · Answer

Well, your’re right of course, but he won’t be able to see the impedance of the MISO line in his logic analyzer, only the level it happens to have, which would be 0V if the line hasn’t been charged before

aripod · Answer

Hello @irina_kim, @Eugeny and @Philipp_K, I went back to this project and I see that the pulses over MISO are out of sync with SCLK and their width is shorter than SCLK’s period. In this thread it is more clear. Any help will be much appreciated. Thanks