W5500 reset timing - Do I need to wait after LOW pulse?
Ethernet Chips
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RE: W5500 reset timing - Do I need to wait after LOW pulse?
by Eugeny ·
Where did you find 50 ms? 5.5.1 “reset timing” states that you should have reset signal active for at least Trc=500 us (but if you wish you can have it 50 ms), and then you have to wait for at least Tpl=1 ms until PLL stabilizes.
RE: W5500 reset timing - Do I need to wait after LOW pulse?
by sofakng ·
Thanks for the reply.
I was referring to this comment:
[quote]User need to wait for 50ms after this pin is changed to HIGH to communicate with WIZ850io. (Refer to 5. Timing Diagram)[/quote] as found here: wizwiki.net/wiki/doku.php?id=pro … 50io:start
RE: W5500 reset timing - Do I need to wait after LOW pulse?
by Eugeny ·
If you would look into datasheet for the W5500 chip, you will see than TPL is 1 ms, not 50 ms. This is a question to the people who write datasheets and design chips.
Anyway, ss soon as you use this specific module, to be 100% correct from spec point of view comply to these 50 ms.
This one is correct:
RSTn -> Low Wait 500us RSTn -> High Wait 50ms (use chip)