Consecutive Bus operation

Question

Hi, In the datasheet of W5300, in ‘AC characteristics’ section, there is Read and Write timing diagrams. These diagram show a single access. But for multiple access, I wonder if it’s possible to let the CS signal active (low) between 2 consecutive access ? And If it’s possible, there is no minimum duration specified for the pulse High of RD signal between the to access (like the tCSn time for the CS signal). In fact with our host controller (MPC5554), if we proceed a 32bit access, it will automatically do 2 16bits consecutive accesses. But in that case, sometime the CS don’t rise between the 2 access, only the RD signal rise and stay high only for 15 ns. The addresses also change on the rising of RD. I run some tests and It’s seems to work fine, but would be sure of that point. If there is some doubt about that , I would stick to 16bits read/write, since there is no way on that controller to add extra-time between the 2 accesses. Guillaume.

lawrence · Answer

Hello, barrey. I do not use W5300, but i hope this is helpful for your wonder. Before that, there is my question with your mention. In fact with our host controller (MPC5554), if we proceed a 32bit access, it will automatically do 2 16bits consecutive accesses. -It means you want to access two w5300 with a your 32-bits cpu(mpc5554)?? Then, here is an answer with below words. "But in that case, sometime the CS don’t rise between the 2 access, only the RD signal rise and stay high only for 15 ns. The addresses also change on the rising of RD. " W5300 supports burst mode, so you can read or write addr & data consecutively. But the point is CS and RD/WR status. Offically, W5300 notice CS’ active low and RD/WR’ active low to read/write. If you do consecutively, you need to toggle RD/WR signal(with CS signal active low continuously) to make CS & RD/WR active low at the same time as the timing diagram in w5300 DS. And I suggest the pulse high of RD’ duration is longer than tDATAh + tDATAhe. Thank you, Lawrence.

barrey · Answer

Hi and thanks for your answers, -It means you want to access two w5300 with a your 32-bits cpu(mpc5554)?? No, The external bus is 16 bits wide, and I have only 1 wiznet device wire. I mean that if, in the code, I read (or write) a 32bit data, since the external bus is only 16bits wide, the MPC will automatically proceed with 2 consecutive reads (or wirtes) (of course the MPC increment the address between the 2 access!). In others words, the MPC is able to read (or write) 2 consecutive 16bits registers of the wiznet, in one single code operation, and put that 2 16bits register of the wiznet into one 32bits register of the MPC. W5300 supports burst mode That’s I wanted to know ! [quote]W5300 supports burst mode, so you can read or write addr & data consecutively. But the point is CS and RD/WR status. Offically, W5300 notice CS’ active low and RD/WR’ active low to read/write. If you do consecutively, you need to toggle RD/WR signal(with CS signal active low continuously) to make CS & RD/WR active low at the same time as the timing diagram in w5300 DS.[/quote] That not a problem, when the MPC proceed 2 consecutive access, the CS stay low durring the 2 access, and the RD/WR toggle between the 2 access. And I suggest the pulse high of RD’ duration is longer than tDATAh + tDATAhe. That would be nice to have a confirmation on that point. For the read operation, I have a 15ns pulse on the RD signal, (for Write operation, I have 30ns on WR signal). The question is : tDATAhe value ? Since in my case the MR(RDH) is set to ‘0’ this mean that tDATAhe= 0ns ? So in my case the minimum RD pulse would be tDATAh + tDATAhe = 7ns + 0ns = 7n ? Could you confirm this point ? Thank you.

lawrence · Answer

Hello, barry I am so late… Yes you are right! Only tDATAhe set after MR[RDH] set as ‘1’. And the valid time will be 7ns if tDATAh is 7ns and no MR[RDH] set. thank you lawrence