WIZ550io SPI problems

Question

Hi There I am integrating a WIZ550io with a TI CC3200 but I am having trouble communicating with it over SPI. I have connected the WIZ550io to my target system and ported the ioLibrary_BSD to the CC3200 code base. When connected to our network I can successfully ping the default IP (192.168.1.2) so I know the the WIZ550io is properly powered and running In code I reset the WIZ550io by pulling the RST pin low for 250ms and the RDY pin goes high about 30ms after that so the WIZ550io appears to be properly reset (I have verified this via logic analyzer). About 500ms after the WIZ550io is ready (RDY high) I attempt to read the VERSIONR register by calling… WIZCHIP_READ_BUF(VERSIONR, &tempByte, 1); I always read back 0x01, I am expecting 0x04. CLK is 100KHz and set to SPI mode 0 See the logic analyzer capture below… 1546×849 191 KB A few questions about this capture. Why do I always get 0x01 in MISO for every 8 bits clocked in? Is this correct? No matter what I send out MOSI I always get 0x01 in MISO for every 8 CLK cycles. Does this indicate anything? I was expecting the CS line to remain low during the entire SPI frame (as indicated in w5500 data sheet section 2.3.2 figure 11) however _BSD controls the CS line and it raises CS between every 8 bits. Is this correct? Could it be adding to my communication problems? Can you verify that the VersionR read going out MOSI is correct? It appears to be correct except that the last byte (the MISO read) is 0x01 instead of 0x04. I have tried reading other registers (RTR and RCR) but get similar results and always read out 0x01. I have been trying to get this working for several days now and really need some support on how to proceed next. Thanks Steve

Coccoliso · Answer

Hi, it could be an SPI setting problem and after several attempts I am certain that with these settings the W5500 is working properly: SPI Clock Idle Low SPI Clock Edge On Rising SPI Sample On End I do not use your MPU but see if your SPI is set so, I also had your results when SPI was not set correctly.