W5100 interrupt driven server
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RE: W5100 interrupt driven server
by hjjeon0608 ·
Hi,
First, connect interrupt pin of W5100 to MCU.
Second, set interrupt mask register(IMR) you want to use.
Third, set interrupt in your MCU.
The third step is found at ATMEL MCU datasheet.
RE: W5100 interrupt driven server
by jgmdesigns ·
Thanks for telling me what I already posted.
What I am asking is if there is any code examples that are using the interrupts? Everything I have found on the web has been polling mode only.
I am looking to have the micro only interrupted when the W5100 has made a connection, but I am guessing that it does not have that capability.
JIm
RE: W5100 interrupt driven server
by scowell ·
I have W5100 working with ISR… you have to set the IMR register to allow INT. Of course, you have to set a good MAC/IP/Mask/Port too. If you can ping it, then these are OK… ping is the first step. No ping, no go.
Now you need to make sure your uP interrupt is working OK. Breakpoint in your ISR, then use a wire to short the /INT pin… if you don’t get a break in your ISR then that part is not working. Get your uP ISR going.
Next make sure you have set your socket’s IER and IMR correctly. The pseudo-code in the manual details this.
Here’s my wiz_init():
void init_wiz()
{
}
… here’s my enable_int():
void enable_socket_int()
{
// set IMR register to allow socket 0 interrupts only
put_data_at_address(WIZ_IMR,1);// 1,2,4,8 is socket 0,1,2,3
}
and here’s my wiz.h (this should have been available long ago, I had to make this):
// WIZ constant defines
#define WIZ_TXBUFADDR 0x4000 // W5100 Send Buffer Base Address
#define WIZ_RXBUFADDR 0x6000 // W5100 Read Buffer Base Address
#define WIZ_MAXBUF 0x1FFF
#define WIZ_MAXBUF_PLUSONE 0x2000
//WIZ Register defines
// common registers
#define WIZ_MR 0x0000 //Mode (MR)
// gateway address
#define WIZ_GAR0 0x0001
#define WIZ_GAR1 0x0002
#define WIZ_GAR2 0x0003
#define WIZ_GAR3 0x0004
// subnet mask address
#define WIZ_SUBR0 0x0005
#define WIZ_SUBR1 0x0006
#define WIZ_SUBR2 0x0007
#define WIZ_SUBR3 0x0008
// Source Hardware Address
#define WIZ_SHAR0 0x0009
#define WIZ_SHAR1 0x000A
#define WIZ_SHAR2 0x000B
#define WIZ_SHAR3 0x000C
#define WIZ_SHAR4 0x000D
#define WIZ_SHAR5 0x000E
//Source IP Address
#define WIZ_SIPR0 0x000F
#define WIZ_SIPR1 0x0010
#define WIZ_SIPR2 0x0011
#define WIZ_SIPR3 0x0012
//0x0013 Reserved
//0x0014 Reserved
// Interrupt (IR)
#define WIZ_IR 0x0015
//Interrupt Mask (IMR)
#define WIZ_IMR 0x0016
// Retry Time
#define WIZ_RTR0 0x0017
#define WIZ_RTR1 0x0018
// Retry Count (RCR)
#define WIZ_RCR 0x0019
// RX Memory Size (RMSR)
#define WIZ_RMSR 0x001A
// TX Memory Size (TMSR)
#define WIZ_TMSR 0x001B
// Authentication Type in PPPoE
#define WIZ_PATR0 0x001C
#define WIZ_PATR1 0x001D
// Reserved
// 0x001E
// ~
// 0x0027
// PPP LCP Request Timer
#define WIZ_PTIMER 0x0028
// PPP LCP Magic number
#define WIZ_PMAGIC 0x0029
// Unreachable IP Address
#define WIZ_UIPR0 0x002A
#define WIZ_UIPR1 0x002B
#define WIZ_UIPR2 0x002C
#define WIZ_UIPR3 0x002D
// Unreachable Port
#define WIZ_UPORT0 0x002E
#define WIZ_UPORT1 0x002F
//Reserved
//0x0030-3FF
// socket 0
#define WIZ_S0_MR 0x0400 //Socket 0 Mode (S0_MR)
#define WIZ_S0_CR 0x0401 //Socket 0 Command (S0_CR)
#define WIZ_S0_IR 0x0402 //Socket 0 Interrupt (S0_IR)
#define WIZ_S0_SR 0x0403 //Socket 0 Status (S0_SR)
//Socket 0 Source Port
#define WIZ_S0_PORT0 0x0404
#define WIZ_S0_PORT1 0x0405
//Socket 0 Destination Hardware Address
#define WIZ_S0_DHAR0 0x0406
#define WIZ_S0_DHAR1 0x0407
#define WIZ_S0_DHAR2 0x0408
#define WIZ_S0_DHAR3 0x0409
#define WIZ_S0_DHAR4 0x040A
#define WIZ_S0_DHAR5 0x040B
//Socket 0 Destination IP Address
#define WIZ_S0_DIPR0 0x040C
#define WIZ_S0_DIPR1 0x040D
#define WIZ_S0_DIPR2 0x040E
#define WIZ_S0_DIPR3 0x040F
//Socket 0 Destination Port
#define WIZ_S0_DPORT0 0x0410
#define WIZ_S0_DPORT1 0x0411
//Socket 0 Maximum Segment Size
#define WIZ_S0_MSSR0 0x0412
#define WIZ_S0_MSSR1 0x0413
//Socket 0 Protocol in IP Raw mode
#define S0_PROTO 0x0414
#define WIZ_S0_TOS 0x0415 //Socket 0 IP TOS (S0_TOS)
#define WIZ_S0_TTL 0x0416 //Socket 0 IP TTL (S0_TTL)
//Reserved
//0x0417-F
//Socket 0 TX Free Size
#define WIZ_S0_TX_FSR0 0x0420
#define WIZ_S0_TX_FSR1 0x0421
//Socket 0 TX Read Pointer
#define WIZ_S0_TX_RD0 0x0422
#define WIZ_S0_TX_RD1 0x0423
//Socket 0 TX Write Pointer
#define WIZ_S0_TX_WR0 0x0424
#define WIZ_S0_TX_WR1 0x0425
//Socket 0 RX Received Size
#define WIZ_S0_RX_RSR0 0x0426
#define WIZ_S0_RX_RSR1 0x0427
//Socket 0 RX Read Pointer
#define WIZ_S0_RX_RD0 0x0428
#define WIZ_S0_RX_RD1 0x0429
//Reserved
//0x042A-FF
// socket 1
#define WIZ_S1_MR 0x0500 //Socket 1 Mode (S1_MR)
#define WIZ_S1_CR 0x0501 //Socket 1 Command (S1_CR)
#define WIZ_S1_IR 0x0502 //Socket 1 Interrupt (S1_IR)
#define WIZ_S1_SR 0x0503 //Socket 1 Status (S1_SR)
//Socket 1 Source Port
#define WIZ_S1_PORT0 0x0504
#define WIZ_S1_PORT1 0x0505
//Socket 1 Destination Hardware Address
#define WIZ_S1_DHAR0 0x0506
#define WIZ_S1_DHAR1 0x0507
#define WIZ_S1_DHAR2 0x0508
#define WIZ_S1_DHAR3 0x0509
#define WIZ_S1_DHAR4 0x050A
#define WIZ_S1_DHAR5 0x050B
//Socket 1 Destination IP Address
#define WIZ_S1_DIPR0 0x050C
#define WIZ_S1_DIPR1 0x050D
#define WIZ_S1_DIPR2 0x050E
#define WIZ_S1_DIPR3 0x050F
//Socket 1 Destination Port
#define WIZ_S1_DPORT0 0x0510
#define WIZ_S1_DPORT1 0x0511
//Socket 1 Maximum Segment Size
#define WIZ_S1_MSSR0 0x0512
#define WIZ_S1_MSSR1 0x0513
//Socket 1 Protocol in IP Raw mode
#define WIZ_S1_PROTO 0x0514
#define WIZ_S1_TOS 0x0515 //Socket 1 IP TOS (S1_TOS)
#define WIZ_S1_TTL 0x0516 //Socket 1 IP TTL (S1_TTL)
//Reserved
//0x0517-F
//Socket 1 TX Free Size
#define WIZ_S1_TX_FSR0 0x0520
#define WIZ_S1_TX_FSR1 0x0521
//Socket 1 TX Read Pointer
#define WIZ_S1_TX_RD0 0x0522
#define WIZ_S1_TX_RD1 0x0523
//Socket 1 TX Write Pointer
#define WIZ_S1_TX_WR0 0x0524
#define WIZ_S1_TX_WR1 0x0525
//Socket 1 RX Received Size
#define WIZ_S1_RX_RSR0 0x0526
#define WIZ_S1_RX_RSR1 0x0527
//Socket 1 RX Read Pointer
#define WIZ_S1_RX_RD0 0x0528
#define WIZ_S1_RX_RD1 0x0529
//Reserved
//0x052A-FF
// Socket 2
#define WIZ_S2_MR 0x0600 //Socket 2 Mode (S2_MR)
#define WIZ_S2_CR 0x0601 //Socket 2 Command (S2_CR)
#define WIZ_S2_IR 0x0602 //Socket 2 Interrupt (S2_IR)
#define WIZ_S2_SR 0x0603 //Socket 2 Status (S2_SR)
//Socket 2 Source Port
#define WIZ_S2_PORT0 0x0604
#define WIZ_S2_PORT1 0x0605
//Socket 2 Destination Hardware Address
#define WIZ_S2_DHAR0 0x0606
#define WIZ_S2_DHAR1 0x0607
#define WIZ_S2_DHAR2 0x0608
#define WIZ_S2_DHAR3 0x0609
#define WIZ_S2_DHAR4 0x060A
#define WIZ_S2_DHAR5 0x060B
//Socket 2 Destination IP Address
#define WIZ_S2_DIPR0 0x060C
#define WIZ_S2_DIPR1 0x060D
#define WIZ_S2_DIPR2 0x060E
#define WIZ_S2_DIPR3 0x060F
//Socket 2 Destination Port
#define WIZ_S2_DPORT0 0x0610
#define WIZ_S2_DPORT1 0x0611
//Socket 2 Maximum Segment Size
#define WIZ_S2_MSSR0 0x0612
#define WIZ_S2_MSSR1 0x0613
//Socket 2 Protocol in IP Raw mode
#define WIZ_S2_PROTO 0x0614
#define WIZ_S2_TOS 0x0615 //Socket 2 IP TOS (S2_TOS)
#define WIZ_S2_TTL 0x0616 //Socket 2 IP TTL (S2_TTL)
//Reserved
//0x0617-F
//Socket 2 TX Free Size
#define WIZ_S2_TX_FSR0 0x0620
#define WIZ_S2_TX_FSR1 0x0621
//Socket 2 TX Read Pointer
#define WIZ_S2_TX_RD0 0x0622
#define WIZ_S2_TX_RD1 0x0623
//Socket 2 TX Write Pointer
#define WIZ_S2_TX_WR0 0x0624
#define WIZ_S2_TX_WR1 0x0625
//Socket 2 RX Received Size
#define WIZ_S2_RX_RSR0 0x0626
#define WIZ_S2_RX_RSR1 0x0627
//Socket 2 RX Read Pointer
#define WIZ_S2_RX_RD0 0x0628
#define WIZ_S2_RX_RD1 0x0629
//Reserved
//0x062A-0x06FF
// Socket 3
#define WIZ_S3_MR 0x0700 //Socket 3 Mode (S3_MR)
#define WIZ_S3_CR 0x0701 //Socket 3 Command (S3_CR)
#define WIZ_S3_IR 0x0702 //Socket 3 Interrupt (S3_IR)
#define WIZ_S3_SR 0x0703 //Socket 3 Status (S3_SR)
//Socket 3 Source Port
#define WIZ_S3_PORT0 0x0704
#define WIZ_S3_PORT1 0x0705
//Socket 3 Destination Hardware Address
#define WIZ_S3_DHAR0 0x0706
#define WIZ_S3_DHAR1 0x0707
#define WIZ_S3_DHAR2 0x0708
#define WIZ_S3_DHAR3 0x0709
#define WIZ_S3_DHAR4 0x070A
#define WIZ_S3_DHAR5 0x070B
//Socket 3 Destination IP Address
#define WIZ_S3_DIPR0 0x070C
#define WIZ_S3_DIPR1 0x070D
#define WIZ_S3_DIPR2 0x070E
#define WIZ_S3_DIPR3 0x070F
//Socket 3 Destination Port
#define WIZ_S3_DPORT0 0x0710
#define WIZ_S3_DPORT1 0x0711
//Socket 3 Maximum Segment Size
#define WIZ_S3_MSSR0 0x0712
#define WIZ_S3_MSSR1 0x0713
//Socket 3 Protocol in IP Raw mode
#define WIZ_S3_PROTO 0x0714
#define WIZ_S3_TOS 0x0715 //Socket 3 IP TOS (S3_TOS)
#define WIZ_S3_TTL 0x0716 //Socket 3 IP TTL (S3_TTL)
//Reserved
//0x0717-F
//Socket 3 TX Free Size
#define WIZ_S3_TX_FSR0 0x0720
#define WIZ_S3_TX_FSR1 0x0721
//Socket 3 TX Read Pointer
#define WIZ_S3_TX_RD0 0x0722
#define WIZ_S3_TX_RD1 0x0723
//Socket 3 TX Write Pointer
#define WIZ_S3_TX_WR0 0x0724
#define WIZ_S3_TX_WR1 0x0725
//Socket 3 RX Received Size
#define WIZ_S3_RX_RSR0 0x0726
#define WIZ_S3_RX_RSR1 0x0727
//Socket 3 RX Read Pointer
#define WIZ_S3_RX_RD0 0x0728
#define WIZ_S3_RX_RD1 0x0729
//Reserved
//0x072A ~ 0x07FF
// S0_CR values (commands)
#define WIZ_CR_OPEN 0x01 // Initialize or open socket
#define WIZ_CR_LISTEN 0x02 // Wait connection request in tcp mode(Server mode)
#define WIZ_CR_CONNECT 0x04 // Send connection request in tcp mode(Client mode)
#define WIZ_CR_DISCON 0x08 // Send closing reqeuset in tcp mode
#define WIZ_CR_CLOSE 0x10 // Close socket
#define WIZ_CR_SEND 0x20 // Update Tx memory pointer and send data
#define WIZ_CR_SEND_MAC 0x21 // Send data with MAC address, so without ARP process
#define WIZ_CR_SEND_KEEP 0x22 // Send keep alive message
#define WIZ_CR_RECV 0x40 // Update Rx memory buffer pointer and receive data
extern uint8_t sockState;
// S0_SR values (statuses)
#define WIZ_SOCK_CLOSED 0x00 // Closed
#define WIZ_SOCK_INIT 0x13 // Init state
#define WIZ_SOCK_LISTEN 0x14 // Listen state
#define WIZ_SOCK_SYNSENT 0x15 // Connection state
#define WIZ_SOCK_SYNRECV 0x16 // Connection state
#define WIZ_SOCK_ESTABLISHED 0x17 // Success to connect
#define WIZ_SOCK_FIN_WAIT 0x18 // Closing state
#define WIZ_SOCK_CLOSING 0x1A // Closing state
#define WIZ_SOCK_TIME_WAIT 0x1B // Closing state
#define WIZ_SOCK_CLOSE_WAIT 0x1C // Closing state
#define WIZ_SOCK_LAST_ACK 0x1D // Closing state
#define WIZ_SOCK_UDP 0x22 // UDP socket
#define WIZ_SOCK_IPRAW 0x32 // IP raw mode socket
#define WIZ_SOCK_MACRAW 0x42 // MAC raw mode socket
#define WIZ_SOCK_PPPOE 0x5F // PPPOE socket
RE: W5100 interrupt driven server
by Speeder ·
Hi Scowell,
I had a look at your post. We are having trouble with the same interrupt topic.
When you initialise the iterrupt you appear only to write to IMR.
How do we choose what action to interrupt on? We want an interrupt when the W1500 receives data from the internet.
What we get now is an interrupt when we send data from the uP to the W1500.
Andrew
RE: W5100 interrupt driven server
by Coccoliso ·
You must set the bit to 1 for the socket that you want to check in the IMR register (page 22 bit IM_IR0 / IM_IR3) then receiving interrupt read the IR register (pages 21 and 22) and with the S0_INT / S3_INT bits can see which socket has generated the interrupt.
Now for every Sn_INT bit at 1 ( with n from 0 to 3) test the interrupt cause reading Sn_IR socket register (page 27 / 28) :
SEND_OK (bit 4)
TIMEOUT (bit 3)
RECV (bit 2) < This is your case
DISCON (bit 1)
CON (bit 0)