Wiznet makers

1. What This Project Does

This project implements a multi-channel, high-resolution data acquisition device that reads analog signals through the AD7779 ADC and streams the digitized data to a host PC over Ethernet using TCP.

From the repository description:

Data acquisition device based on STM32H743IIT6 board with SDRAM and EVAL-AD7779FMCZ board with TCP data transition to PC via W5500 board. AD7779 drivers based on https://github.com/Aperture-Electronic/AD7779-Library-STM32/tree/master repository

The system architecture follows a straightforward pipeline:

The firmware is written in C using the STM32 HAL library, developed in STM32CubeIDE (confirmed by the .ioc and .cproject files in the repository). The AD7779 driver layer is adapted from the open-source AD7779-Library-STM32 project, which provides SPI-mode register access for the AD777x family.

2. Why an 8-Channel 24-Bit Σ-Δ ADC Matters

The AD7779 from Analog Devices is not an ordinary ADC. It integrates eight full Σ-Δ ADC channels with simultaneous sampling, meaning all channels are digitized at the same instant — critical for applications where phase relationships between signals matter (power quality monitoring, vibration analysis, multi-axis sensor fusion).

Key AD7779 capabilities relevant to this project:

• 24-bit resolution with up to 16 kSPS per channel in high-resolution mode
• Per-channel programmable gain amplifier (PGA): gains of ×1, ×2, ×4, ×8 map low-amplitude sensor outputs into the ADC's full-scale range
• Ultra-low input current (±1.5 nA differential) enabling direct sensor connection without external buffering
• On-chip sinc3 digital filter with sample rate converter (SRC) for flexible output data rate tuning
• Built-in 12-bit SAR ADC for system diagnostics without sacrificing Σ-Δ channels
• Internal 2.5 V reference (10 ppm/°C typical) or external reference support up to 3.6 V

The EVAL-AD7779FMCZ evaluation board used in this project provides a ready-made analog front end with proper power supply decoupling, reference circuitry, and FMC connector pinout — reducing the barrier to integrating this precision ADC into a custom system.

3. Why W5500 Makes Sense for DAQ Data Streaming

Choosing the WIZnet W5500 for Ethernet connectivity in a DAQ system is a deliberate engineering decision, not just a convenience:

Hardwired TCP/IP offload eliminates software stack overhead. The STM32H743 is a powerful Cortex-M7 MCU, but in a DAQ application, every CPU cycle matters. With 8 channels × 24 bits × up to 16 kSPS, the data throughput can reach significant levels. The W5500's hardware TCP/IP stack handles segmentation, retransmission, and flow control entirely in silicon, freeing the MCU to focus on what it does best: reading ADC data and managing the acquisition pipeline.

Deterministic network behavior. Software TCP/IP stacks (lwIP, etc.) introduce variable latency from interrupt handling, buffer management, and protocol processing. The W5500's hardwired approach provides more predictable timing — an important characteristic when streaming continuous ADC data that must arrive at the PC without gaps or reordering.

Simple SPI interface. The W5500 connects to the STM32 via SPI, keeping the hardware integration minimal. No external PHY, no MAC configuration, no MDIO management — just SPI commands to open a socket, write data, and the W5500 handles the rest.

8 independent hardware sockets. The W5500 supports 8 simultaneous TCP/UDP sockets, which could allow future expansion such as separate data streams per ADC channel, a control channel alongside the data channel, or concurrent connections from multiple monitoring PCs.

4. The Role of SDRAM in High-Throughput Acquisition

The STM32H743IIT6 board includes external SDRAM, which plays a critical role in bridging the speed mismatch between the ADC data rate and the network transmission rate. The STM32H743 can buffer large blocks of ADC samples in SDRAM before transmitting them over TCP via the W5500, preventing data loss during network congestion or socket busy periods.

The STM32H743 itself is well-suited for this role — it features a Cortex-M7 core running at up to 480 MHz, a flexible memory controller (FMC) for SDRAM interfacing, multiple SPI peripherals for parallel ADC and Ethernet communication, and DMA controllers that can move data between peripherals and memory with minimal CPU intervention.

FAQ

Q1: What is the AD7779 and why use it for data acquisition? The AD7779 is an 8-channel, 24-bit simultaneous sampling Σ-Δ ADC from Analog Devices. It features per-channel programmable gain (×1/2/4/8), ultra-low input current for direct sensor connection, an on-chip sinc3 filter, and a 12-bit SAR ADC for diagnostics. It is well-suited for multi-channel precision measurement applications like power quality analysis, vibration monitoring, and industrial sensor arrays.

Q2: How does the W5500 handle TCP data streaming from the STM32? The W5500 is connected to the STM32H743 via SPI. The MCU writes ADC data into the W5500's socket transmit buffer, and the W5500's hardwired TCP/IP engine handles packetization, acknowledgment, and retransmission autonomously. This offloads all networking overhead from the MCU, allowing it to focus on continuous ADC data acquisition.

Q3: What sample rate can this system achieve? The AD7779 supports up to 16 kSPS per channel in high-resolution mode and up to 8 kSPS in low-power mode, simultaneously across all 8 channels. The achievable system throughput depends on the SPI clock speeds, SDRAM buffering strategy, and W5500 TCP transmission rate configured in the firmware.

Q4: Can I use a W5500-based board like WIZnet W5500-EVB-Pico or W5100S instead? The project uses a W5500 module connected via SPI. Any W5500-based board that exposes the SPI interface should be compatible with appropriate pin mapping. The W5100S could also work as it shares a similar SPI command structure, though socket buffer sizes differ.

Q5: Why use SDRAM buffering instead of streaming directly? At full speed, 8 channels × 24 bits × 16 kSPS generates approximately 3 Mbps of raw ADC data. Network transmission is inherently bursty — TCP acknowledgments, retransmissions, and socket buffer management can introduce momentary pauses. SDRAM provides a large buffer (typically megabytes) to absorb these pauses and prevent sample loss.

Q6: What development environment does this project use? The project is built with STM32CubeIDE, as indicated by the .ioc configuration file and .cproject project files in the repository. The firmware is written in C using the STM32 HAL library.

Q7: Is this project production-ready or a development prototype? Based on the repository structure, this is a development/prototype project. It uses the Analog Devices EVAL-AD7779FMCZ evaluation board rather than a custom PCB, and the repository has minimal documentation. It serves as a solid reference design demonstrating the integration of a high-precision ADC with Ethernet-based data streaming using the W5500.