The Design about Interface of Ethernet Based on FPGA and W5500
The Design about Interface of Ethernet Based on FPGA and W5500
Abstract:
Expounding the application of NIOS Ⅱ and W5500 on the interface of Ethernet，and how to design the structure of hardware and the software of NOIS Ⅱ .
NIOS Ⅱ core:
>There are two ways to develop Ethernet interfaces in FPGA. One is to directly write interface programs through FPGA logic gates or verilog and other languages. However, the process is extremely cumbersome and error-prone, resulting in unstable network transmission and no possibility for further development and expansion in the future. benefit. The second way is through the NIOS Ⅱ soft core method. NIOS Ⅱ is a soft core processor (that is, MCU) developed by Altera Company specifically for Altera's series of FPGAs. However, it is a soft core and needs to be added manually according to specific needs. Add After that, you will get a NIOS Ⅱ processor in the FPGA). The software development for NIOS Ⅱ is based on C, C++ language or assembly language. The software development environment is the NIOS Ⅱ IDE supporting Qartus2. NIOS II is a soft core. In the concept of FPGA, the so-called software is to embed a CPU inside the FPGA to control the FPGA to complete system work. However, these tasks are generally simple interface programs and cannot bring out the true effectiveness of the FPGA. It's different with NIOS II. NIOS II is like embedding a CPU like a microcontroller or DSP inside the FPGA, which can complete very complex system functions. And when the entire control system is expanded or upgraded in the future, just replace the FPGA with a higher-end, more resource-rich model.
HW structure:
> FPGA + W5500
> Also includes analog signal acquisition and coordination FPGA is a CPU
chip that performs algorithm processing.
Programming block diagram:
> After powering on, NIOS II first initializes the Ethernet, connects to the W5500 through the SPI bus, and determines whether the network connection is successful. After the network connection is successful, the required basic parameters are loaded into the FPGA interface module, and the While loop in the main function is started to continuously make various judgments. When an interrupt is generated, data collection and transmission through the interrupt function are started.
Conclusion:
The Ethernet design using NIOS II soft core not only ensures the real-time performance of Ethernet data transmission, but also lays a good foundation for future system expansion. It provides a very good solution for the current Ethernet control system in the automated testing industry solution.