How to Build an 80 MHz SPI TCP Client with WIZnet W5500 on FPGA?
This education-focused project uses Verilog FPGA logic to control a WIZnet W5500 as a multi-socket TCP client.
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Project description
How to Build an 80 MHz SPI TCP Client with WIZnet W5500 on FPGA? Summary This education-focused project uses Verilog FPGA logic to control a WIZnet W5500 as a multi-socket TCP client. The source describes a 160 MHz FPGA system clock, an 80 MHz W5500 SPI clock, support for all eight hardware sockets, and state-machine-based initialization, interrupt polling, transmission, and reception. W5500 provides the Ethernet MAC/PHY, hardwired TCP/IP processing, socket state machines, retransmission handling, and 32 KB packet memory. The FPGA implements the host-side SPI controller, register sequencer…
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