Embedded system Ethernet gateway design based on W5500
Embedded system Ethernet gateway design based on W5500
Abstract:
An embedded system Ethernet gateway design scheme based on the network chip W5500 was designed, the hardware design and software design were introduced in detail, the circuit schematic and key initialization configurations were given, and the designed gateway was tested. This solution is simple to implement, has a short development cycle, and has low cost. It is a good choice for the design of Ethernet gateways for embedded systems.
Contents:
- HW design:
> W5500 + HR91105A(Hanrun RJ45)
-SW design:
> The initialization content includes the following parts:
3. Set the repeated transmission timeout register and the repeated transmission count register. After the chip is initialized and configured, it can check the gateway server for Socket settings. In the data sending and receiving processing, a conditional sending and interrupt receiving strategy is adopted. After the receipt is sent and received, the gateway server is rechecked for Socket settings. This cycle is the software design flow chart of the entire gateway as the picture shows.
Set the designed Ethernet gateway to TCP client mode, set the server on the PC, connect the two through a network cable, and install a network debugging assistant on the PC to observe the test results. The microcontroller will regularly send the string "istdoit" to the PC through the Ethernet gateway designed in this article. The PC can also send data to the microcontroller. After the microcontroller receives the data, it will send the received data to the PC. Through the network debugging assistant on the PC, you can determine whether the designed gateway is sending and receiving data normally. The test results are shown in picture.
Conclusion:
This article introduces the design of an embedded Ethernet gateway based on W5500. After experimental verification, this solution can realize Ethernet communication simply and flexibly, and has good stability and real-time performance. This solution has a short development cycle, low cost, and is easy to implement. It is especially suitable for low-level processors with small RAM and can greatly shorten the product development cycle.