Sharing SPI bus – discussion involving W5500 on the Raspberry Pi Pico
A maker described a hardware scenario where two SPI devices (W5500 Ethernet module) share the same MOSI/MISO/CLK lines but have separate chip-select (CS) pins.
🔍 Overview
A maker on the Raspberry Pi forums described a hardware scenario in which two SPI devices (one being the W5500 Ethernet module) share the same MOSI/MISO/CLK lines but have separate chip-select (CS) pins. The discussion evolves into a deep technical conversation around whether this is viable, what constraints exist on the SPI bus for the RP2040/Pico environment, and how W5500 performs in that scenario.
💬 Key Discussion Points
The original poster wrote: “I am intending to use SPI#0 for a Wiznet W5500 module (wired ethernet), and … I’m designing carrier boards which I can plug a Pico into, along with the TFT and Wiznet modules.”
A reply from a user named “stevend” noted: “As a general rule I would avoid sharing pins as you are proposing … results may be unpredictable …”
Another user “gmx” commented on how outputs replicate signal to multiple pins and inputs combine signals (OR logic), pointing to potential shared-line risk.
One useful note: someone mentioned that the W5500 “works pretty well with the Pico2, provided you can live with maximum 8 open connections.”
🛠 WIZnet Insights
From this discussion, we can draw several practical design and use-case takeaways for WIZnet’s maker audience:
Shared SPI bus caution
While MOSI/MISO/CLK lines can be shared across devices, the CS line must be managed rigorously.
If one slave device’s CS remains asserted or improper timing is used, interference or bus contention may occur.
For W5500 applications: prefer dedicated CS pin, or ensure your board design uses a controlled 1-to-n decoder/logic to switch CS cleanly (as suggested in the thread: “via a 1 to 2 line decoder using logic ICs”).
Device performance limits with W5500
A community member points out that with the Pico2 + W5500 setup, one can expect up to about 8 TCP sockets open — this aligns with W5500’s documented eight-socket limit.
For high-performance or many-connection use-cases, designers should verify whether the W6100/6300 family (or an alternative board architecture) might be more suitable.
Design tip: bus speed & logic isolation
Since multiple devices share the bus, set a safe SPI clock (e.g., ≤ 30 MHz) to maintain signal integrity.
Use logic gates or decoders if you anticipate mixing high-speed devices or shared lines across modules.
Confirm that CS toggles correctly via oscilloscope or logic analyzer during debug (CS not toggling = device silent).