Wiznet makers

Base Project

     https://github.com/WIZnet-ioNIC/WIZnet-PICO-AZURE-C

#define ADC_NUM 0
#define ADC_PIN (26 + ADC_NUM)
#define ADC_VREF 3.3
#define ADC_RANGE (1 << 12)
#define ADC_CONVERT (ADC_VREF / (ADC_RANGE - 1))
#define ADC_CLK_VAL 2999

stdio_init_all();
printf("Beep boop, listening...\n");
bi_decl(bi_program_description("Analog microphone example for Raspberry Pi Pico")); // for picotool

adc_fifo_setup(
true,    // Write each completed conversion to the sample FIFO
true,    // Enable DMA data request (DREQ)
1,       // DREQ (and IRQ) asserted when at least 1 sample present
true,   // We won't see the ERR bit because of 8 bit reads; disable.
false // Shift each sample to 8 bits when pushing to FIFO
);

adc_set_clkdiv(ADC_CLK_VAL);//2999= 16kS/s

This explanation describes the process of setting up the sampling rate for an ADC (Analog-to-Digital Converter).

Base Clock:
The ADC clock (ADC CLK) is set to 48 MHz.

Divider:
To reduce the ADC sampling rate, a divider is used. The divider takes the input clock and divides it by a specified value to determine the actual sampling rate of the ADC.

Divider Calculation:
The divider is set to 1 + 2999, where 2999 is the user-defined value. Therefore, the divider is calculated as follows:

1. $$\text{ADC Divider} = 1 + 2999 = 3000$$

Sampling Rate Calculation:
The ADC sampling rate is determined by dividing the input clock by the divider.

1. $$\text{ADC Sampling Rate} = \frac{48 \text{ MHz}}{3000} = 16 \text{ kS/s}$$

Through this calculation, the ADC is configured to sample at a rate of 16,000 samples per second (16 kS/s).

In summary, by dividing the 48 MHz clock by 3000, a sampling rate of 16 kS/s is achieved. This sampling rate is chosen based on the required resolution for digitizing the signal.

Before using the Raspberry Pi board, we will first work on the W55RP20 board and microphone component.