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gavinchang

Published July 12, 2026 ©

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How to Synchronize RTC Time with WIZnet W5500 on STM32?

This education and maker project uses WIZnet W5500 on an STM32 platform to build wired Ethernet communication with NTP-based RTC time synchronization.

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PROJECT DESCRIPTION

How to Synchronize RTC Time with WIZnet W5500 on STM32?

Summary

This education and maker project uses WIZnet W5500 on an STM32 platform to build wired Ethernet communication with NTP-based RTC time synchronization. The GitCode project describes STM32 integration with W5500, Ethernet driver porting, NTP time synchronization for accurate RTC calibration, and USART DMA reception for efficient variable-length serial data handling. W5500 provides the Ethernet MAC/PHY, hardwired TCP/IP stack, socket engine, and internal Tx/Rx buffering, while STM32 firmware handles RTC logic, NTP workflow, USART DMA, diagnostics, and application behavior.

What the Project Does

The project is an STM32 + W5500 Ethernet development and time-synchronization toolkit. Its main function is to integrate a W5500 Ethernet controller into an STM32 project, port the Ethernet-related driver files, use NTP to calibrate the STM32 RTC, and extend USART reception with DMA for efficient arbitrary-length data handling. The related GitCode blog describes the project structure as including driver code, examples, documents, libraries, and include files.

The practical data flow is:

STM32 application → Ethernet driver and W5500 socket layer → SPI → W5500 → RJ45 Ethernet → router or gateway → NTP server → RTC update inside STM32 firmware.

For education, this project is useful because it connects several embedded concepts in one workflow: SPI peripheral bring-up, Ethernet controller initialization, socket-based UDP communication, NTP packet exchange, RTC calibration, serial debugging, and DMA-based reception. For maker use, it gives a practical base for network clocks, timestamped sensor nodes, data loggers, lab instruments, home automation devices, and local monitoring tools.

Where WIZnet Fits

The exact WIZnet product is W5500. It sits between the STM32 and the Ethernet connector. STM32 communicates with W5500 through SPI, chip select, reset, and optionally interrupt. W5500 handles Ethernet MAC/PHY operation, hardwired TCP/IP processing, socket state transitions, and packet buffering.

W5500 is a hardwired TCP/IP Internet controller with SPI access up to 80 MHz. It integrates a 10/100 Ethernet MAC and PHY, supports TCP, UDP, ICMP, IPv4, ARP, IGMP, and PPPoE, provides 8 independent sockets, and includes 32 KB internal memory for Tx/Rx buffers. WIZnet also lists SNTP among the supported services in its W5500 software resources, which directly matches the time-synchronization direction of this project.

This division is useful on STM32 because the firmware can focus on timekeeping, RTC update rules, UART/DMA behavior, and application logic while W5500 owns the lower Ethernet transport boundary. For an NTP design, that boundary is important: the firmware should form and parse NTP messages, but W5500 should handle the wired Ethernet link, UDP socket behavior, ARP/IP handling, and packet buffering.

Implementation Notes

The GitCode page confirms the STM32 + W5500 Ethernet and NTP synchronization project, but the visible repository page did not expose inspectable source files during verification. Therefore, no project-specific source code from the GitCode archive is quoted here. The snippets below are verified reference snippets from WIZnet’s official ioLibrary_Driver, which WIZnet lists as an official W5500 software resource.

File: Ethernet/wizchip_conf.h
What it configures: WIZnet chip selection and W5500 SPI interface mode.
Why it matters: this is the firmware boundary where an STM32 project selects W5500 and confirms that the host interface is SPI before Ethernet, UDP, or NTP behavior can work.

 
#define W5100 5100 #define W5100S 5100+5 #define W5200 5200 #define W5300 5300 #define W5500 5500 #define W6100 6100

#elif (_WIZCHIP_ == W5500) #define _WIZCHIP_ID_ "W5500\0"

#ifndef _WIZCHIP_IO_MODE_ #define _WIZCHIP_IO_MODE_ _WIZCHIP_IO_MODE_SPI_ #endif
 

The official configuration header defines W5500 as a supported WIZnet chip and selects SPI as the W5500 interface mode when no other interface mode is defined.

File: Ethernet/W5500/w5500.h
What it configures: W5500 local IP access and socket-state access.
Why it matters: an NTP/RTC project needs to distinguish network setup problems from time-protocol problems. Local IP configuration, socket status, Tx buffer space, Rx received size, and PHY state should be visible in logs.

 
#define setSIPR(sipr) \
    WIZCHIP_WRITE_BUF(SIPR, sipr, 4)

#define getSIPR(sipr) \
    WIZCHIP_READ_BUF(SIPR, sipr, 4)

#define setSn_MR(sn, mr) \
    WIZCHIP_WRITE(Sn_MR(sn),mr)

#define getSn_SR(sn) \
    WIZCHIP_READ(Sn_SR(sn))
 

The W5500 header provides register access for local IP address and socket status. Those functions are useful when a maker or student needs to confirm whether a failed NTP update is caused by IP configuration, socket state, cable/link behavior, DNS/NTP reachability, or RTC update logic.

Practical Tips / Pitfalls

  • Verify SPI access and W5500 identity before debugging NTP or RTC behavior.
  • Use UDP for NTP traffic and keep the NTP socket separate from other demo sockets.
  • Route W5500 reset to an STM32 GPIO so firmware can recover Ethernet without rebooting the whole board.
  • Log local IP, gateway, DNS/NTP server address, socket status, RTC value before update, RTC value after update, and last synchronization error.
  • Treat USART DMA as a separate performance path; do not let serial reception buffers corrupt Ethernet or NTP timing tests.
  • Test NTP server unreachable, cable removal, DHCP failure, duplicate IP, router reboot, and RTC drift after long idle time.
  • Keep the first maker demo simple: Ethernet link, IP address, one NTP query, RTC update, then timestamped serial or sensor output.

FAQ

Q: Why use WIZnet W5500 for STM32 RTC time synchronization?
A: W5500 gives STM32 a wired Ethernet interface with hardwired TCP/IP, 8 sockets, and 32 KB internal Tx/Rx memory. That lets STM32 firmware focus on NTP message handling, RTC calibration, USART DMA reception, diagnostics, and application behavior while W5500 handles Ethernet MAC/PHY operation, UDP transport, socket state, and buffering.

Q: How does W5500 connect to the STM32 platform?
A: W5500 connects through SPI using SCLK, MOSI, MISO, chip select, reset, 3.3 V, and ground. Interrupt is optional for a simple polling demo, but it is useful when receive, timeout, or disconnect events should be handled without constant polling.

Q: What role does W5500 play in this project?
A: W5500 is the wired Ethernet transport engine for the NTP workflow. STM32 builds the time-synchronization logic and updates RTC state; W5500 manages Ethernet MAC/PHY behavior, hardwired TCP/IP processing, UDP socket state, and packet buffering.

Q: Can beginners follow this project?
A: Yes, if the work is staged. The recommended order is STM32 project import, SPI wiring check, W5500 reset check, IP configuration, UDP socket test, NTP query, RTC update, USART DMA validation, and then a final timestamped maker application.

Q: How does W5500 compare with Wi-Fi for time-synchronized maker nodes?
A: Wi-Fi is better when the device must avoid cabling. W5500 is better when the lesson or prototype needs a visible wired link, explicit reset control, stable bench behavior, and easier separation of SPI, PHY, IP, UDP, NTP, and RTC faults. For education and maker projects, that visibility often matters more than wireless convenience.

Source

Original source: GitCode repository “基于STM32W5500的以太网功能开发与时间同步方案: STM32W5500以太网开发与NTP时间同步工具包.” The visible page states that the project integrates W5500 with STM32, ports Ethernet driver files, uses NTP for RTC time synchronization, extends USART with DMA reception, and lists an MIT license link.

Related GitCode blog: “基于STM32 + W5500的以太网功能开发与时间同步方案.” The article describes the project overview, technical points, application scenarios, file-structure overview, quick-start steps, and debugging notes for W5500 Ethernet, NTP RTC synchronization, and USART DMA reception.

WIZnet product reference: W5500 documentation and feature list, including hardwired TCP/IP, SPI up to 80 MHz, embedded 10/100 Ethernet MAC/PHY, 8 sockets, 32 KB internal buffer memory, and supported software services including SNTP.

WIZnet driver reference: official ioLibrary_Driver, including W5500 chip selection, SPI interface configuration, register access, socket control, and supported network services.

Tags

#W5500 #WIZnet #STM32 #NTP #RTC #Education #Maker #Ethernet #SPI #Firmware #Performance #USARTDMA #Socket #EmbeddedNetworking

STM32에서 WIZnet W5500으로 RTC 시간을 동기화하는 방법은?

요약

이 교육 및 maker 프로젝트는 STM32 플랫폼에서 WIZnet W5500을 사용해 NTP 기반 RTC time synchronization을 포함한 유선 Ethernet 통신을 구축합니다. GitCode 프로젝트는 STM32와 W5500의 통합, Ethernet driver porting, 정확한 RTC calibration을 위한 NTP time synchronization, 효율적인 variable-length serial data handling을 위한 USART DMA reception을 설명합니다. W5500은 Ethernet MAC/PHY, hardwired TCP/IP stack, socket engine, internal Tx/Rx buffering을 제공하고, STM32 firmware는 RTC logic, NTP workflow, USART DMA, diagnostics, application behavior를 담당합니다.

프로젝트가 하는 일

이 프로젝트는 STM32 + W5500 Ethernet development 및 time-synchronization toolkit입니다. 주요 기능은 W5500 Ethernet controller를 STM32 project에 통합하고, Ethernet 관련 driver file을 porting하며, NTP를 사용해 STM32 RTC를 보정하고, USART reception을 DMA로 확장해 임의 길이 데이터를 효율적으로 처리하는 것입니다. 관련 GitCode blog는 project structure가 driver code, example, document, library, include file을 포함한다고 설명합니다.

실제 데이터 흐름은 다음과 같습니다.

STM32 application → Ethernet driver and W5500 socket layer → SPI → W5500 → RJ45 Ethernet → router 또는 gateway → NTP server → STM32 firmware 내부 RTC update

교육용으로 이 프로젝트는 여러 embedded concept을 하나의 workflow로 연결하기 때문에 유용합니다. SPI peripheral bring-up, Ethernet controller initialization, socket-based UDP communication, NTP packet exchange, RTC calibration, serial debugging, DMA-based reception을 함께 다룰 수 있습니다. Maker 용도로는 network clock, timestamped sensor node, data logger, lab instrument, home automation device, local monitoring tool의 기반이 됩니다.

WIZnet이 들어가는 위치

이 프로젝트에서 사용되는 정확한 WIZnet 제품은 W5500입니다. W5500은 STM32와 Ethernet connector 사이에 위치합니다. STM32는 SPI, chip select, reset, 선택적으로 interrupt를 통해 W5500과 통신합니다. W5500은 Ethernet MAC/PHY operation, hardwired TCP/IP processing, socket state transition, packet buffering을 처리합니다.

W5500은 최대 80 MHz SPI access를 지원하는 hardwired TCP/IP Internet controller입니다. 10/100 Ethernet MAC and PHY를 통합하고, TCP, UDP, ICMP, IPv4, ARP, IGMP, PPPoE를 지원하며, 8개 independent socket과 Tx/Rx buffer용 32 KB internal memory를 포함합니다. WIZnet은 W5500 software resource에서 SNTP를 supported service로 제시하며, 이는 이 프로젝트의 time-synchronization 방향과 직접 연결됩니다.

이 분업은 STM32에서 유용합니다. Firmware는 timekeeping, RTC update rule, UART/DMA behavior, application logic에 집중할 수 있고, W5500은 하위 Ethernet transport boundary를 담당합니다. NTP 설계에서는 이 경계가 중요합니다. Firmware는 NTP message를 만들고 해석해야 하지만, W5500은 wired Ethernet link, UDP socket behavior, ARP/IP handling, packet buffering을 처리해야 합니다.

구현 참고 사항

GitCode page는 STM32 + W5500 Ethernet 및 NTP synchronization project임을 확인할 수 있지만, visible repository page는 검증 중 inspect 가능한 source file을 노출하지 않았습니다. 따라서 GitCode archive의 프로젝트별 source code는 인용하지 않습니다. 아래 snippet은 WIZnet이 공식 W5500 software resource로 제공하는 ioLibrary_Driver에서 가져온 검증된 reference snippet입니다.

파일: Ethernet/wizchip_conf.h
설정 내용: WIZnet chip selection 및 W5500 SPI interface mode
중요한 이유: STM32 project가 W5500을 선택하고 host interface가 SPI임을 확인하는 firmware boundary입니다. Ethernet, UDP, NTP 동작은 이 하위 계층이 먼저 안정적으로 동작해야 가능합니다.

 
#define W5100 5100 #define W5100S 5100+5 #define W5200 5200 #define W5300 5300 #define W5500 5500 #define W6100 6100

#elif (_WIZCHIP_ == W5500) #define _WIZCHIP_ID_ "W5500\0"

#ifndef _WIZCHIP_IO_MODE_ #define _WIZCHIP_IO_MODE_ _WIZCHIP_IO_MODE_SPI_ #endif
 

공식 configuration header는 W5500을 supported WIZnet chip으로 정의하고, 다른 interface mode가 정의되지 않았을 때 W5500 interface mode를 SPI로 선택합니다.

파일: Ethernet/W5500/w5500.h
설정 내용: W5500 local IP access 및 socket-state access
중요한 이유: NTP/RTC 프로젝트는 network setup problem과 time-protocol problem을 구분해야 합니다. Local IP configuration, socket status, Tx buffer space, Rx received size, PHY state는 log에서 확인 가능해야 합니다.

 
#define setSIPR(sipr) \
    WIZCHIP_WRITE_BUF(SIPR, sipr, 4)

#define getSIPR(sipr) \
    WIZCHIP_READ_BUF(SIPR, sipr, 4)

#define setSn_MR(sn, mr) \
    WIZCHIP_WRITE(Sn_MR(sn),mr)

#define getSn_SR(sn) \
    WIZCHIP_READ(Sn_SR(sn))
 

W5500 header는 local IP address와 socket status를 위한 register access를 제공합니다. 이러한 function은 maker나 학생이 NTP update 실패 원인을 IP configuration, socket state, cable/link behavior, DNS/NTP reachability, RTC update logic 중 어디에서 찾아야 하는지 확인하는 데 유용합니다.

실무 팁 / 주의점

  • NTP 또는 RTC behavior를 debug하기 전에 SPI access와 W5500 identity를 먼저 검증해야 합니다.
  • NTP traffic에는 UDP를 사용하고, NTP socket은 다른 demo socket과 분리하는 것이 좋습니다.
  • W5500 reset은 STM32 GPIO에 연결해 전체 board를 reboot하지 않고 Ethernet을 복구할 수 있게 해야 합니다.
  • Local IP, gateway, DNS/NTP server address, socket status, RTC value before update, RTC value after update, last synchronization error를 기록해야 합니다.
  • USART DMA는 별도의 performance path로 다뤄야 합니다. Serial reception buffer가 Ethernet 또는 NTP timing test를 망가뜨리면 안 됩니다.
  • NTP server unreachable, cable removal, DHCP failure, duplicate IP, router reboot, long idle time 이후 RTC drift를 테스트해야 합니다.
  • 첫 maker demo는 단순하게 유지하는 것이 좋습니다. Ethernet link, IP address, one NTP query, RTC update, timestamped serial 또는 sensor output 순서가 적합합니다.

FAQ

Q: STM32 RTC time synchronization에 왜 WIZnet W5500을 사용하나요?
A: W5500은 STM32에 hardwired TCP/IP, 8개 socket, 32 KB internal Tx/Rx memory를 갖춘 유선 Ethernet interface를 제공합니다. 따라서 STM32 firmware는 NTP message handling, RTC calibration, USART DMA reception, diagnostics, application behavior에 집중하고, W5500은 Ethernet MAC/PHY operation, UDP transport, socket state, buffering을 처리합니다.

Q: W5500은 STM32 platform에 어떻게 연결되나요?
A: W5500은 SCLK, MOSI, MISO, chip select, reset, 3.3 V, ground를 사용하는 SPI로 연결됩니다. Interrupt는 단순 polling demo에서는 선택 사항일 수 있지만, receive, timeout, disconnect event를 constant polling 없이 처리해야 할 때 유용합니다.

Q: 이 프로젝트에서 W5500은 어떤 역할을 하나요?
A: W5500은 NTP workflow를 위한 유선 Ethernet transport engine입니다. STM32는 time-synchronization logic을 만들고 RTC state를 업데이트합니다. W5500은 Ethernet MAC/PHY behavior, hardwired TCP/IP processing, UDP socket state, packet buffering을 관리합니다.

Q: 초보자도 이 프로젝트를 따라갈 수 있나요?
A: 가능합니다. 다만 단계적으로 진행해야 합니다. 권장 순서는 STM32 project import, SPI wiring check, W5500 reset check, IP configuration, UDP socket test, NTP query, RTC update, USART DMA validation, 그다음 timestamped maker application 구현입니다.

Q: Time-synchronized maker node에서 W5500은 Wi-Fi와 비교하면 어떤 차이가 있나요?
A: Wi-Fi는 device가 cable을 피해야 할 때 더 적합합니다. W5500은 visible wired link, explicit reset control, stable bench behavior, SPI, PHY, IP, UDP, NTP, RTC fault를 쉽게 분리할 수 있는 구조가 필요할 때 더 적합합니다. Education 및 maker project에서는 이런 가시성이 wireless convenience보다 더 중요한 경우가 많습니다.

출처

Original source: GitCode repository “基于STM32W5500的以太网功能开发与时间同步方案: STM32W5500以太网开发与NTP时间同步工具包.” Visible page는 project가 W5500을 STM32와 통합하고, Ethernet driver file을 porting하며, NTP를 RTC time synchronization에 사용하고, USART를 DMA reception으로 확장한다고 설명합니다. 또한 MIT license link를 표시합니다.
https://gitcode.com/open-source-toolkit/60355

Related GitCode blog: “基于STM32 + W5500的以太网功能开发与时间同步方案.” 해당 article은 W5500 Ethernet, NTP RTC synchronization, USART DMA reception을 위한 project overview, technical point, application scenario, file-structure overview, quick-start step, debugging note를 설명합니다.
https://blog.gitcode.com/d63c1c838614c099c8baa11933a53cb2.html

WIZnet product reference: W5500 documentation and feature list, including hardwired TCP/IP, SPI up to 80 MHz, embedded 10/100 Ethernet MAC/PHY, 8 sockets, 32 KB internal buffer memory, and supported software services including SNTP.
https://docs.wiznet.io/Product/Chip/Ethernet/W5500

WIZnet driver reference: official ioLibrary_Driver, including W5500 chip selection, SPI interface configuration, register access, socket control, and supported network services.
https://github.com/Wiznet/ioLibrary_Driver

태그

#W5500 #WIZnet #STM32 #NTP #RTC #Education #Maker #Ethernet #SPI #Firmware #Performance #USARTDMA #Socket #EmbeddedNetworking

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