W5500 Ethernet PHY transceiver: Sharing the SPI bus with W5500 and an MFRC522
Ethernet Chips
- W5500
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Ethernet Chips
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RE: W5500 Ethernet PHY transceiver: Sharing the SPI bus with W5500 and an MFRC522
by TheoIm WIZnet ·
Hi,
When sharing the same SPI bus, it is important to verify whether the CS timing margins (setup/hold) are properly maintained at the moment MISO data is being driven. This should be checked using an oscilloscope or logic analyzer.
In theory, this configuration is feasible. However, when issues occur, they are typically caused by CS timing violations or MISO line contention.
If the problem can be reproduced, it would be very helpful if you could capture and share the following signals:
Additionally, if you have a case where the system operates normally, please provide the corresponding code or SPI control method. This will help with comparative analysis.
Thank you