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The advanced high-performance bus (AHB) protocol enforces a strict timeout mechanism, which interrupts data transfer if a slave device fails to respond within a specified period. This constraint severely hinders efficient communication between AHB and low-speed peripherals such as those using the external memory interface (EMIF), leading to prolonged processor occupation, wasted computational resources, and systemic performance degradation. To address this incompatibility, this paper proposes a novel bus-coupling architecture that allows the AHB to operate in a high-speed, zero-delay mode while ensuring seamless communication with low-speed EMIF peripherals. The proposed solution includes a Zero-Delay Controller and its corresponding software driver to facilitate integration and operation. The design was implemented in Verilog HDL and validated on a domestic Jingwei Qili H7-series Field-Programmable Gate Array platform under a 200-MHz processor clock and a 70-MHz peripheral clock. Experimental results show that a single atomic access consumed only 2 clock cycles with zero wait states, achieving a 98% reduction in access latency compared with conventional schemes. Each read operation saved 22 clock cycles, and each write saved 21 cycles. Cumulative savings reached 2398 cycles for reads and 2100 cycles for writes over 100 consecutive transfers. Greater performance gains were observed with peripherals operating at even lower frequencies. This design significantly enhances the applicability of high-performance, multicore ARM processors in edge computing embedded systems.