Adding Ethernet to a Retro Computer — The Open-Source 8/16-bit SBC X65, Powered by W6100

An open-source single-board computer (SBC) running a real 1980s-era 8/16-bit CPU, extended with Ethernet connectivity using the WIZnet W6100.

The X65 is a project that pairs a 6502-family CPU — the same kind found in vintage game consoles and home computers — with modern components to build a fully functional machine from scratch. Video, audio, storage, and networking are all integrated on a single board, with every design file and line of source code publicly available under the MIT license. Networking is handled by the WIZnet W6100, which offloads TCP/IP processing entirely to hardware, leaving the CPU free for application logic.

Background: The Rise of DIY Retro Computing

Among developers with a love for 1980s 8-bit computers, a growing movement has emerged that goes beyond running emulators — people are designing and building real hardware from scratch. One such project is X65, started in 2023 by Czech developer Jaroslav Sýkora.

X65 is a single-board computer built around the WDC W65C816S (16-bit) or W65C02S (8-bit) CPU — the same processor family that powered the SNES and the Apple IIGS. Like a Raspberry Pi, it integrates CPU, video, audio, storage, and networking on one board, but with a 6502-family CPU at its core instead of a modern ARM or RISC-V chip. All schematics, Verilog source code, and PCB design files are released under the MIT license, making it fully open for anyone to build or contribute to.

The GitHub repository Maverick-Shark/X65_BigMiST is a derivative project that ports the original X65 to run on a MiST FPGA development board, removing the need to build the physical PCB.

WIZnet's Role: Bringing TCP/IP to a Retro System with W6100

Networking on the X65 is handled entirely by the WIZnet W6100. W6100 is a hardwired TCP/IP Ethernet controller that enables socket communication through simple register reads and writes — no software protocol stack required on the CPU side.

Why a Hardwired TCP/IP Chip Was Needed

The X65's CPU (W65C816S) runs at 8MHz. Unlike modern MCUs, it simply does not have the headroom to run a software TCP/IP stack such as LwIP. Offloading protocol handling to dedicated hardware was not optional — it was a hard requirement. WIZnet's Hardwired TCP/IP architecture was a precise fit for this constraint.

Why W6100 Instead of W5500

The W5500 is WIZnet's most widely used Ethernet chip. X65 chose the more capable W6100 for two specific reasons:

• Parallel bus interface: The 6502 CPU architecture uses a traditional parallel address/data bus. W6100 supports parallel bus mode natively, allowing it to connect directly to the CPU bus without an additional SPI controller. W5500, being SPI-only, would have required extra glue logic to fit this architecture.
• IPv6 support: Even on a retro platform, the designers chose W6100 to ensure compatibility with modern network environments at the hardware level — a practical decision for longevity and future extensibility.

How It Works: W6100 Connected via Parallel Bus

The W6100 is connected to the CPU through the NORA FPGA (the system controller) using Indirect Bus Mode — a parallel bus access method.

Four control registers are mapped into the CPU's I/O address space at $9F80–$9F83:

Software accesses the full W6100 register space — socket registers, TX/RX buffers, and common registers — entirely through these four addresses. This means TCP/UDP sockets can be opened and data can be transferred using 6502 assembly or C code.

The overall system architecture looks like this:

[W65C816 CPU] — bus — [NORA FPGA (System Controller)]
                              ├── [VERA FPGA]  → VGA output
                              ├── [AURA FPGA]  → Stereo audio (FM + PSG)
                              ├── [2MB SRAM]
                              ├── [W6100]      → Ethernet RJ45 (10/100Mbps)
                              └── [SDHC / PS/2 / SNES Controllers]

NORA acts as the system's north bridge, handling address decoding and chip select signals, and transparently connecting W6100 to the CPU bus.

Why This Is New

W6100 has been used in many ARM and RISC-V based projects, but its application on a 6502/65816-based retro computing platform is virtually uncharted territory. Two aspects stand out:

• Platform novelty: A 1980s CPU architecture running W6100's hardwired TCP/IP stack is, to our knowledge, one of the first publicly documented examples of this combination.
• Architectural novelty: Using an FPGA (NORA) as a system controller to bridge a modern Ethernet chip with a retro CPU is an emerging pattern in the embedded retro computing space — and X65 is a clean reference implementation of this approach.

Where This Could Go

The X65 architecture has clear potential beyond retro hobbyist use:

• Networked retro gaming: Building on Commander X16 (CX16) software compatibility, Ethernet enables multiplayer games, leaderboards, and online ROM distribution.
• Embedded education: The stack-free, bare-metal nature of the platform makes it ideal for teaching CPU architecture, assembly language, interrupt handling, and socket programming — all the way down to the hardware.
• Legacy system networking: The 6502 family is still in use in safety-critical industries. X65 serves as a reference design for adding Ethernet to low-power 6502-based systems without burdening the CPU.
• FPGA prototyping: The Maverick-Shark/X65_BigMiST fork shows that the design can run on commercial FPGA boards without custom PCBs, lowering the barrier to experimentation and deployment.

Tech Stack Summary

FAQ

Q. Does the X65 require the physical PCB to run? No. The Maverick-Shark/X65_BigMiST fork ports the X65 to the MiST FPGA development board, so you can run the system without building custom hardware. That said, the W6100 Ethernet chip is part of the physical SBC design — networking functionality in the FPGA-only version depends on how the port is implemented.

Q. Can the W6100 be replaced with a W5500? Not without redesigning the interface logic. W5500 is SPI-only, while X65 uses W6100's parallel bus mode to connect directly to the CPU's address/data bus. Switching to W5500 would require adding an SPI controller (e.g., via the NORA FPGA) and rewriting the low-level driver, effectively increasing design complexity with no clear benefit.

Q. Is IPv6 actually useful on an 8/16-bit retro computer? Practically speaking, IPv4 covers most use cases today. However, having IPv6 support at the hardware level in W6100 means the system remains compatible with modern networks without any software-side protocol implementation. It also future-proofs the design as IPv6-only environments become more common.

Q. How does software communicate with W6100 on the X65? Through four I/O registers mapped at $9F80–$9F83 in the CPU's address space. The software writes a target address to IDM_ARH/ARL and a block selector to IDM_BSR, then reads or writes data through IDM_DR. This indirect addressing scheme lets a 16-bit CPU access W6100's full 32 KB internal register/buffer space with minimal overhead.

Q. Can existing Commander X16 (CX16) software run on the X65? Yes, with some caveats. X65 is software-compatible with the CX16 — it can run unmodified CX16 programs. However, the official CX16 ROM is proprietary and licensed only for use on CX16 hardware, so it is not included in the X65 project. The W6100 Ethernet interface and certain other hardware features (e.g., no Commodore IEC port) are X65-specific and require dedicated software support.

Project Links

• Original project: jsyk/X65 · Project site: http://www.x65.eu
• MiST FPGA port: Maverick-Shark/X65_BigMiST
• WIZnet W6100 product page: https://www.wiznet.io/product-item/w6100/