---
title: "The Design Proposal Aerospace Electronic Test Equipment based on Multi-interface Data Communication"
url: "https://maker.wiznet.io/siva_ranjeet/projects/the-design-proposal-aerospace-electronic-test-equipment-based-on-multi-interface-data-communication/"
markdown_url: "https://maker.wiznet.io/siva_ranjeet/projects/the-design-proposal-aerospace-electronic-test-equipment-based-on-multi-interface-data-communication/md"
type: "UCC: User Created Content"
author: "Yan Jun Zhang, Wen Sheng Qiao, Jin Ling Wang"
author_url: "https://www.scientific.net/AMM.336-338.3"
editor: "WIZnet"
editor_url: "https://maker.wiznet.io/"
original_author: "Yan Jun Zhang, Wen Sheng Qiao, Jin Ling Wang"
original_url: "https://www.scientific.net/AMM.336-338.3"
published: "2022-10-11"
language: "en"
likes: 5
views: 1168
comments: 0
source: "WIZnet Makers (https://maker.wiznet.io/)"
---

# The Design Proposal Aerospace Electronic Test Equipment based on Multi-interface Data Communication

> Project has been applied for engineering practice & improves the efficiency of the design of the remote measurement equipment & maintenance

Original author: Yan Jun Zhang, Wen Sheng Qiao, Jin Ling Wang (source: https://www.scientific.net/AMM.336-338.3)

## Article

#### Introduction

With the raising of aerospace remote measurement technology totally, the application of the new technology in electronics, communications, computers and the virtual test technology, putting a higher requirement to the maintenance and testing of the various electronic devices, Although various spacecraft remote measurement electronic devices (such as the signal source) are quite different in functions, according to the test content, it can be summarized as the following functions: issuing commands, returning the states and test data, from the perspective of the remote measurement equipment several common test content, this paper design a set of generic remote measurement equipment internal data transfer protocol. In this way, a variety of remote measurement equipments share a set of internal protocol, and it can improve the efficiency and maintenance of the remote equipments. The paper focuses on the versatility, formulates the data transfer protocol which allows the data to be transmission internally.it streamlines or expands the agreement according to actual needs.

#### Design Program

**The Test model and the bus **

The entire remote measurement system is made up with the testing device and the target device, the terminal of test console includes console, data link layer and the test interface. It is shown in Fig.1,this design is the protocols of data interaction which are between the control equipment to test equipment. The measuring instruments are almost based on different standards of the bus, the module design is essentially the design of the system bus architecture. The test system of this paper has 4 forms:

1. PCI bus

2. USB bus

3. RS422 bus

4. Ethernet bus.

![](https://maker.wiznet.io/upload/ckeditor5/490413977%5F1665510598%2Epng)

**Total solutions **

FPGA is the master chip of the test interface in test equipment, the external SRAM memory and the FPGA internal RAM can store control words and data, such as HM628512,this paper defined register in the internal FPGA, storing control words and data which are used in the test interface. These control words and data are transmitted by the control device, the test interface has used the following four categories, which can be returned the control of the states and data equipment. In this way, the interaction between the control and elementary equipment completely converse the data transmission, It is shown in Fig.2.

#### Control equipment interface

**The PCI interface **

Industrial control computer is acting as a controlling device in this design. This is a PCI interface, a way is drawn by the PCI bus bridge chip. This way can provide a 32 bit wide data interface; it is beneficial to achieve independent FPGA internal registers bus address and data lines. The high 16 bit of the 32 bit interfaces is acted as the address bus, for addressing the FPGA internal registers, the lower 16 bits as the data bus, transmission control equipment issued or upload the data or commands in this paper design.

![](https://maker.wiznet.io/upload/ckeditor5/490413977%5F1665510952%2Epng)

This article uses the PCI bridge chip PCI9054,which is produced by PLX company, its local bus has 3 mode of operations: M,C,J mode, the design uses the 32 bit local bus, the data and address do not used multiplex, so choose C mode. The C mode provides the local bus interface which is easy to use, uses simple interface timing convenient data I/O. The is interface timing is achieved by FPGA. At the same time,PCI9054 local bus interface is implemented in the FPGA internal registers (is shown in Table 1),as well as data exchange interface and test equipment, it is shown in Fig.3.

![](https://maker.wiznet.io/upload/ckeditor5/490413977%5F1665510977%2Epng)

The working process is as follows: the data processing unit transmit a 32 bit effective data through the PCI interface to the PCI9054,The FPGA controls PCI9054 local bus to get the 32 bit valid data and plus the start bit and verification bit comprises 40 bit command word .And sending the data to the test system by an asynchronous serial. When it returns data to the test system, the FPGA also receives 40 bit packet in the same manner and is obtained by decoding the 32 bit effective data saved to the internal FIFO buffer, then read the internal FIFO control PCI9054 local bus to upload data to the data processing unit.

**USB-FIFO interface **

In this article, we use industrial control computer as a control device, the second interface is FT245RL,the article designed the interface circuit, including the USB protocol chip FT245RL and FPGA, which realizes the communication between PC and FPGA. Interface circuit is shown in Fig.4. The working principle: FT245RL transmits the data with the microcontroller, which controls RXF # TXF #,RD #,WR through the 8 bit parallel data port, AD [0:7] and four read-write state. Because this way can provide an 8 bit wide data interface ,this article multiplexed address bus and data bus, flag is '1',then receives the address, the data are read from the FT245RL,flag is '0' then receiving the data. Part of the VHDL code as follows:

![](https://maker.wiznet.io/upload/ckeditor5/490413977%5F1665511518%2Epng)

It is shown in Fig.5,In accordance with the reading timing of FT245RL,current FIFO receives buffer data when RXF # is low. Then reading buffer data by performing a read operation, FIFO controller export 8 bit data port through receiving buffer data when the RD from high to low, When RD # signal goes high, the data reading is completed, At this time there will be a short-term high-level in RXF #.This means FT245RL is processing the read operation, then goes low, can read the next byte data. When it is fully read FIFO through receiving buffer data, which prohibited to read data from the FIFO receiving buffer When RXF# is empty.

![](https://maker.wiznet.io/upload/ckeditor5/490413977%5F1665511595%2Epng)

**RS422 interface **

In addition, we use PCI 1612 card, the exported data connected with RS422 interface by the way of asynchronous serial, the data width of RS422 interface is 5 to 8 bit, with an 8 bit wide data interface. This article multiplexed address bus and data bus, flag is '1',then receive the address, data are read from the register, flag is '0' then receive data. Part of the VHDL code as follows:

![](https://maker.wiznet.io/upload/ckeditor5/490413977%5F1665511673%2Epng)

**Ethernet interface **

The fourth bus mode is Ethernet bus,W5300 is master chip, interface circuit is shown in Fig.6,W5300 and the host interface has two modes, that is direct address mode and indirect address, bus has a 16 bit and 8 bit two modes. W5300 configuration as 16 bit bus direct address mode,8 bit as an address,8 bit as the data in this article,W5300 data bus and address bus connected to the FPGA I/O interface.

**Data link **

For PCI interface program, a lot of data these are measured, we can put them distributing in the other functional blocks. In this way, a backplane will be needed, which is used to contact the forward data function and pass data to the function of the board between the PCI card. For each function board FPGA herein, it is used to control the interface register, which is distributed in the FPGA internal. When control device is sending data to find address, first addressing board card number, and then addressing the board FPGA internally defined register address. In Table 1,the local bus address 0x00 corresponding the FPGA registers bus interface "meaning can be changed to: the highest 8 bit expressed the board address, the second highest 8 bit expressed the register address in the board's FPGA internal, the low 16 bit expressed sending valid data. The basic architecture of the data link is shown in Fig.7.

![](https://maker.wiznet.io/upload/ckeditor5/490413977%5F1665512671%2Epng)

**Communication between the board and the agreement **

Taking into account the rate factor, we use LVDS for communication between the PCI card and backplane. FPGA clock generally tens of MHz, in order to achieve the transmission rate of several tens of megabytes per second, we use a serializer, deserializer as LVDS chip. The article use DS92LV1023,DS92LV1224,which allows access 66MHz clock data width is 10,well positioned to meet the design requirements. on the sending end, so that the signal can be transmitted over longer distances through the use of the cable high-speed drive CLC001.on the receiving side, so that the signal transmitted by using the adaptive equalizer CLC014 equalizer. part of LVDS circuit is shown in Fig.8 and Fig.9.

![](https://maker.wiznet.io/upload/ckeditor5/490413977%5F1665512807%2Epng)

LVDS data port the higher 2 bits indicates the data types, the lower 8 bits represent valid data."00" indicates an invalid number,"01" represents the command,"10" indicates the state,"11" indicates the data. it is implemented data analyzing and converting by FPGA.

LVDS communication is suitable for high data rate card and low rate card with RS422 communication.RS422 communication using asynchronous serial, serial data packets with LVDS data port conversion is as follows: above distinguish the kind of data the LVDS high 2 bits data, which as RS422 data packets mode domain, and 32 valid data as data domain, coupled with the start bit, verify bit, stop bit constitute RS422 serial data packets, is shown in table 2.

![](https://maker.wiznet.io/upload/ckeditor5/490413977%5F1665512916%2Epng)

The conversion relation of the data transfer protocol between the individual boards are shown in Fig.10.Other functional modules, such as analog card data, transceiver board and switch board design will not be discussed.

#### Experimental verification

The programs of the various interfaces and then through the other functional modules, produce analog and digital switch, analog sine waveform is shown in Fig.11, Fig.12.generating a pulse waveform which is shown in Fig.13,Fig.14,the frequency for the 10kHz, 80kHz.

![](https://maker.wiznet.io/upload/ckeditor5/490413977%5F1665513045%2Epng)

![](https://maker.wiznet.io/upload/ckeditor5/490413977%5F1665513133%2Epng)

As can be seen from the above four figures, equipment generates smooth waveform, high precision, and to meet the research requirements.

#### Conclusions

This article completed a set of protocol framework, it is the internal data transmission of the testing equipment used, which has a variety of interfaces, a highly versatile. We can expand or streamline it according to the actual application. The agreement has great practical value to improve the efficiency of the development and maintenance efficiency, the experimental results verify the correctness.

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Source: https://maker.wiznet.io/siva_ranjeet/projects/the-design-proposal-aerospace-electronic-test-equipment-based-on-multi-interface-data-communication/