---
title: "SynthesijerでDE0nanoにWIZ830MJを接続してみた"
url: "https://maker.wiznet.io/scott/projects/synthesijer%E3%81%A7de0nano%E3%81%ABwiz830mj%E3%82%92%E6%8E%A5%E7%B6%9A%E3%81%97%E3%81%A6%E3%81%BF%E3%81%9F/"
markdown_url: "https://maker.wiznet.io/scott/projects/synthesijer%E3%81%A7de0nano%E3%81%ABwiz830mj%E3%82%92%E6%8E%A5%E7%B6%9A%E3%81%97%E3%81%A6%E3%81%BF%E3%81%9F/md"
type: "UCC: User Created Content"
author: "わさらぼ"
author_url: "https://wasa-labo.com/wp/?p=112"
editor: "WIZnet"
editor_url: "https://maker.wiznet.io/"
original_author: "わさらぼ"
original_url: "https://wasa-labo.com/wp/?p=112"
published: "2023-01-02"
language: "ja"
hardware: ["WIZnet W5300"]
likes: 6
views: 666
comments: 3
source: "WIZnet Makers (https://maker.wiznet.io/)"
---

# SynthesijerでDE0nanoにWIZ830MJを接続してみた

> SynthesijerでDE0nanoにWIZ830MJを接続してみた

Original author: わさらぼ (source: https://wasa-labo.com/wp/?p=112)

## Components

- **WIZnet W5300** x 1 ([docs](https://docs.wiznet.io/Product/Chip/Ethernet/W5300))

## Documents and links

- [WIZ830MJ_Test.java](https://github.com/miyo/de0nano/blob/master/wiz830mj/WIZ830MJ_Test.java) (code)

## Article

The W5300 on the WIZ830MJ has an interface that is highly compatible with the processor, with control/status registers and packet storage memory mapped to the memory address space.

If you're a legitimate Altera user, you're probably going to hang on to Nios II, but first (for me) I wrote a control circuit in Synthesijer.

The control code is ↓.
<https://github.com/miyo/de0nano/blob/master/wiz830mj/WIZ830MJ_Test.java>

The W5300 I/F is equivalent to SRAM, so it can be mapped to a Java array, but the read/write methods are defined so that CS, WR, and RD delays can be appropriately emulated. By the way, the read/write data is byte because it is troublesome to solder all the 16bit bus, so 8bit is connected.

The test method actually controls (initializes) the W5300. Here, only network settings are made so that ping can be confirmed.

When synthesizing with Quartus II, use [the code converted to HDL by Synthesijer,](https://github.com/miyo/de0nano/blob/master/wiz830mj/WIZ830MJ_Test.vhd) wiz830mj_iface.vhd corresponding to WIZ830MJ_Iface ( WIZ830MJ_Iface.java ) [instantiated](https://github.com/miyo/de0nano/blob/master/wiz830mj/wiz830mj_iface.vhd)[in](https://github.com/miyo/de0nano/blob/master/wiz830mj/WIZ830MJ_Iface.java) the Java code, and [top.vhd](https://github.com/miyo/de0nano/blob/master/wiz830mj/top.vhd) which is the top module .

Also, the pin constraint is [wiz830mj_test.qsf](https://github.com/miyo/de0nano/blob/master/wiz830mj/wiz830mj_test.qsf) and the clock constraint is [wiz830mj_test.sdc](https://github.com/miyo/de0nano/blob/master/wiz830mj/wiz830mj_test.sdc) .

After synthesizing and writing sof, ping returned safely. You can also see that the MAC address can be obtained with arp.

![](https://wasa-labo.com/wp/wp-content/uploads/2014/11/Screenshot-from-2014-11-05-034342.png)

Now, let's play with TCP and UDP.

---

Source: https://maker.wiznet.io/scott/projects/synthesijer%E3%81%A7de0nano%E3%81%ABwiz830mj%E3%82%92%E6%8E%A5%E7%B6%9A%E3%81%97%E3%81%A6%E3%81%BF%E3%81%9F/