---
title: "w5100s-verilog"
url: "https://maker.wiznet.io/scarlet/projects/w5100s-verilog/"
markdown_url: "https://maker.wiznet.io/scarlet/projects/w5100s-verilog/md"
type: "UCC: User Created Content"
author: "twikor"
author_url: "https://github.com/twikor/w5100s-verilog"
editor: "WIZnet"
editor_url: "https://maker.wiznet.io/"
original_author: "twikor"
original_url: "https://github.com/twikor/w5100s-verilog"
published: "2023-06-16"
language: "en"
likes: 0
views: 407
comments: 0
source: "WIZnet Makers (https://maker.wiznet.io/)"
---

# w5100s-verilog

> w5100s-verilog

Original author: twikor (source: https://github.com/twikor/w5100s-verilog)

## Article

[M_W5100S.**v**](https://github.com/twikor/w5100s-verilog/blob/main/M_W5100S.v)
This code is written in a hardware description language, Verilog HDL, used for modeling and simulating digital logic circuits.

This code forms a part of an FPGA (Field Programmable Gate Array) program used to control the W5100S chip. The W5100S is an Ethernet controller with a built-in hardware TCP/IP stack made by a company called WIZnet. This code implements the interface with the W5100S chip in Verilog. This interface communicates with the W5100S using an SPI (Serial Peripheral Interface).

Falling edge detection: This is a module that detects the falling edge of two signals (at_n, res_int_n) and delays the signals. The falling edge refers to the moment when a digital signal transitions from HIGH to LOW state. This module generates a pulse for one clock cycle each time the input signal has a falling edge.

SPI data reception synchronization: This is a module that synchronizes asynchronous signals and automatically resets the SPI data ready signal.

SPI signal merging: This logic implements the merging of SPI signals coming from the interrupt and main processing state machines. The signals spi_start, spi_wr, spi_data_in are determined by either of the two.

SPI host bus controller: This controls read/write operations to the W5100S using the SPI interface.

Interrupt handling: This implements the interrupt handling state machine. This state machine handles interrupts that occur from the W5100S chip."

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[M_W5100S_SPIMaster.v](https://github.com/twikor/w5100s-verilog/blob/main/M_W5100S_SPIMaster.v)

This code, written in Verilog, is an implementation of SPI (Serial Peripheral Interface) communication, a type of serial communication protocol. SPI is primarily used for serial data transfer between a master and a slave, and this code represents a hardware design that implements this communication protocol.

The code is composed of two main parts: the signal update block and the SPI state machine.

Signal update block:

This block synchronizes with the start signal, ready signal, and reset signal, processes the data, and manages the status flags. The busy flag indicates if the SPI communication is in progress. The busy flag is set when the start signal is activated, and is released when all data transfer is complete. The data_ready flag indicates if the data is ready. The ready signal is activated when data is ready, and it persists until the start signal arrives. The start_flag is used to initiate data transmission. It is set when the start signal is activated and is released when the ready signal is activated. SPI State Machine:

This is a state machine that manages the progress of SPI communication. It manages data transfer in each state and transitions to the next state. In each state, it sets up the MOSI (Master Out Slave In) or MISO (Master In Slave Out), adjusts the data pointer, or transitions to the next state. Data is transferred in units of 32 bits, which is handled through the data_mosi and data_miso registers. This state machine synchronizes with the clk (clock) signal, and all state changes of the SPI occur at the rising edge of the clock

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Source: https://maker.wiznet.io/scarlet/projects/w5100s-verilog/