---
title: "FPGA + W5500 Control Unit"
url: "https://maker.wiznet.io/mark/projects/fpga-w5500-control-unit/"
markdown_url: "https://maker.wiznet.io/mark/projects/fpga-w5500-control-unit/md"
type: "UCC: User Created Content"
author: "mark"
author_url: "https://maker.wiznet.io/mark/"
original_url: "https://www.86ic.net/bandaoti/ic/336687.html"
published: "2023-09-04"
language: "en"
likes: 0
views: 1515
comments: 0
source: "WIZnet Makers (https://maker.wiznet.io/)"
---

# FPGA + W5500 Control Unit

> FPGA + W5500 Control Unit

Original source: https://www.86ic.net/bandaoti/ic/336687.html

## Article

Hardware : Spartan 6 XC6SLX150-2FG484C (168 IOs) + W5500

Software : Verilog

Function: Multi-channel comprehensive test system with FPGA as the central control unit

![](https://maker.wiznet.io/upload/ckeditor5/724090869%5F1693843288%2Epng)

The prototype under test needs to perform cyclic measurement and control of 8 devices under test, and record, interpret, store and forward the measurement data. It uses FPGA as the central control unit for overall program planning. The FPGA control structure block diagram of this system is obtained as shown in Figure 1 below. Show. The main functions to be completed include channel switching control, signal network control, control signal generation, Ethernet data communication, etc.

The layer module summarizes each layer and controls data exchange and other functions. The top layer includes five sub-modules:

1) Clock module, used for clock generation;

2) Data manipulation module, used to manipulate and cache data;

3) The W5500 control module completes the data transmission between the TCP/IP protocol and the PC;

4) The switch control module completes the control of the tested prototype according to the instructions of the PC terminal;

5) STM32 control module, to complete the interaction and control of FPGA and AD network, serial communication, etc.

![](https://maker.wiznet.io/upload/ckeditor5/724090869%5F1693843310%2Epng)

FPGA program planning structure hierarchical diagram

![](https://maker.wiznet.io/upload/ckeditor5/724090869%5F1693843329%2Epng)

System top-level summary RTL schematic diagram

![](https://maker.wiznet.io/upload/ckeditor5/724090869%5F1693843354%2Epng)

![](https://maker.wiznet.io/upload/ckeditor5/724090869%5F1693843365%2Epng)

---

Source: https://maker.wiznet.io/mark/projects/fpga-w5500-control-unit/