---
title: "Controlling the W5500 from a RISC-V Softcore: Ethernet Integration on Basys‑3 FPGA"
url: "https://maker.wiznet.io/josephsr/projects/controlling-the-w5500-from-a-risc-v-softcore-ethernet-integration-on-basys3-fpga/"
markdown_url: "https://maker.wiznet.io/josephsr/projects/controlling-the-w5500-from-a-risc-v-softcore-ethernet-integration-on-basys3-fpga/md"
type: "UCC: User Created Content"
author: "bsoeker"
author_url: "https://github.com/bsoeker/risc-v"
editor: "WIZnet"
editor_url: "https://maker.wiznet.io/"
original_author: "bsoeker"
original_url: "https://github.com/bsoeker/risc-v"
published: "2025-07-30"
language: "en"
hardware: ["RISC-V Internationa RISC-V RV32I"]
likes: 0
views: 1195
comments: 0
source: "WIZnet Makers (https://maker.wiznet.io/)"
---

# Controlling the W5500 from a RISC-V Softcore: Ethernet Integration on Basys‑3 FPGA

> A RISC‑V CPU on an FPGA successfully talks to a W5500 chip via SPI, enabling hardware-based Ethernet with ARP scan detection.

Original author: bsoeker (source: https://github.com/bsoeker/risc-v)

## Components

- **RISC-V Internationa RISC-V RV32I** x 1
- Software: **United States Department of Defense VHDL**

## Article

### 📌 What is This Project?

This project is a **minimal RISC‑V softcore CPU**, implemented in **VHDL** for the **Digilent Basys‑3 FPGA** development board.
It aims to provide a clear, single-cycle implementation of the **RV32I instruction set**, making it ideal for learning architecture and hardware-software integration.

### 🧩 Key Features

**Single-cycle RISC‑V (RV32I) CPU** in VHDL

Toolchain to convert compiled ELF → HEX → VHDL ROM initialization

Fully synthesizable on **Basys‑3 FPGA**

Supports **bare-metal RISC‑V C/Assembly programs**

### 🎯 Educational Focus

Learn instruction-level CPU design

Explore memory-mapped I/O

Simulate real hardware architecture on an FPGA

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Source: https://maker.wiznet.io/josephsr/projects/controlling-the-w5500-from-a-risc-v-softcore-ethernet-integration-on-basys3-fpga/