---
title: "W5500 Interrupts"
url: "https://maker.wiznet.io/forum/9872"
markdown_url: "https://maker.wiznet.io/forum/9872/md"
type: "Forum topic"
category: "Ethernet Chips"
author: "haribabutd"
created: "2014-01-28T10:06:46+09:00"
last_activity: "2017-05-04T08:31:07+09:00"
language: "en"
views: 810
replies: 1
source: "WIZnet Makers forum (https://maker.wiznet.io/forum/)"
---

# W5500 Interrupts

## Question

Asked by haribabutd on 2014-01-28 in Ethernet Chips.

Hi,
I read the datasheet of w5500 and understood the following below.
The protocol i am using is TCP.

1. To enable socket n interrupt, i need to set SIMR and Sn_IMR registers.

2. The interrupt is asserted based upon the value of Sn_IR register which is set by socket APIs.

3. The interrupt is cleared by writing 1 into the particular interrupt bit of Sn_IR register.

Tell me whether my understandings above were correct or not.

With Thanks,
Hari BabU T D.

## Replies

### Reply 1 by hjjeon0608, 2014-01-29

Hi, haribabutd.

1, 3. you understood correctly.

1. I don’t understand your statement.
   Interrupt is asserted by action of chip(packet received, time out occur) and you know it by reading Sn_IR register or signal of INTn pin.

Best regards.

---

Source: https://maker.wiznet.io/forum/9872