---
title: "Unexpected change on MOSI during SPI read of W3150A+"
url: "https://maker.wiznet.io/forum/15645"
markdown_url: "https://maker.wiznet.io/forum/15645/md"
type: "Forum topic"
category: "Ethernet Chips"
author: "jbjbjb"
created: "2025-03-18T10:50:02+09:00"
last_activity: "2025-03-18T10:57:47+09:00"
language: "en"
tags: ["Communication"]
views: 1
replies: 1
source: "WIZnet Makers forum (https://maker.wiznet.io/forum/)"
---

# Unexpected change on MOSI during SPI read of W3150A+

## Question

Asked by jbjbjb on 2025-03-18 in Ethernet Chips.

I am using a W3150A+ part and I am getting an unexpected bit change on the SPI MISO during a read of the RX Received Size Register at address 0x0426 and 0x0427. The unexpected bit change only occurs if I am reading the RX Received Size Register while receiving ethernet traffic.

I normally expect MISO to change only once after each falling edge of SCLK, and most of the time it does. But randomly MISO will instead change after the RISING edge of SCLK.

For example, I get a falling edge on SCLK, then I start sending bit 6 of the RX Received Size Register on MISO, which is currently a logic 0. I then get a rising edge on SCLK, a few nanoseconds later the value of MISO changes to 1. Then the next falling edge of SCLK comes along and MISO goes back to 0 to send the next bit.

Is it possible that if I am sending a bit of the RX Received Size Register on MISO, for example bit 6, and bit 6 updates because the RX Received Size Register value changed (because a new value came into the RX buffer through the ethernet port) before the next falling edge of SCLK, that the MISO signal will update as well, even though I haven't sent the next falling edge of SCLK and MISO?

## Replies

### Reply 1 by jbjbjb, 2025-03-18

I understand that the register contents may dynamically update as packets arrive, but can the dynamically updated contents also be pushed onto MISO and corrupt a bit already in transit to the SPI master?

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Source: https://maker.wiznet.io/forum/15645