---
title: "unexpected data received if RMSR configured"
url: "https://maker.wiznet.io/forum/15008"
markdown_url: "https://maker.wiznet.io/forum/15008/md"
type: "Forum topic"
category: "Ethernet Chips"
author: "zhang-stephen"
created: "2023-08-13T03:42:46+09:00"
last_activity: "2023-08-13T05:26:37+09:00"
language: "en"
views: 167
replies: 0
source: "WIZnet Makers forum (https://maker.wiznet.io/forum/)"
---

# unexpected data received if RMSR configured

## Question

Asked by zhang-stephen on 2023-08-13 in Ethernet Chips.

Hi, I am testing w5300 with a FPGA chip EP4CE10F17C8, which is one of Intel Cyclone IV E series.

The chip configuration:

- Socket 0 enabled as TCP server

- 16-bit data bus

- not aligned in `Sn_MR`

- `TMS01R`= 0x0800, 8kB for Socket 0 and 0kB for Socket 1

- `RMS01R` = 0x0400, 4kB for Socket 0 and 0kB for Socket 1

- `MTYPER` is default

My client sent an ASCII sequence `01100 01100 01100 ` to it. but I received the strange data shown as the screenshot from Quartus SignalTap Logic Analyzer.

[![image](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/0/05f8bcacb5eb1fffb737baec24255c4dc642420c.png) image2468×152 6.74 KB](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/0/05f8bcacb5eb1fffb737baec24255c4dc642420c.png)

You can see the `Sn_RX_FIFOR` data in data bus if the addr bus is `230h`. I think the `c922` is the packet info but it is invalid for me.

But the recevied data is correct if I keep the default of TMS01R and RMS01R, the data is shown in below:

[![image](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/4/43d780e4863c9291d20924e4d3a7626c700a9617.png) image1081×128 3.26 KB](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/4/43d780e4863c9291d20924e4d3a7626c700a9617.png)

Here, the packet-info is 0x0012, 18 bytes, that’s correct. And the following data is expected ASCII sequence.

What’s wrong in my configuration of TMSR or RMSR, and what’s the reason of this issue?

My code could be found [zhang-stephen/ethernet_w5300: Wiznet w5300 driver code, powered by SystemVerilog (github.com)](https://github.com/zhang-stephen/ethernet_w5300), FYI.

---

Source: https://maker.wiznet.io/forum/15008