---
title: "W3150A+ SPI access to TX and RX buffers"
url: "https://maker.wiznet.io/forum/13811"
markdown_url: "https://maker.wiznet.io/forum/13811/md"
type: "Forum topic"
category: "MCU & Boards"
author: "marco"
created: "2020-05-06T08:37:52+09:00"
last_activity: "2020-06-09T13:46:39+09:00"
language: "en"
views: 588
replies: 2
source: "WIZnet Makers forum (https://maker.wiznet.io/forum/)"
---

# W3150A+ SPI access to TX and RX buffers

## Question

Asked by marco on 2020-05-06 in MCU & Boards.

Hello,
using SPI to access the TX and RX buffers of W3150A+ can I assume that the address will be automatically increased after the first 32 bit access (OPCODE(8bit)+ADDRESS(16 bit)+DATA(8 bit)) if I don’t set high the /SS pin allowing me to continue the reception of a new byte only providing 8 new SCLK edges or do I need set high /SS and the low again /SS to perform a complete 32 bit access to the subsequent address in order to perform a new write or read access?
If I need to perform a complete 32 bit access, according the min SCLK period reported in the datasheet (70 ns) I can reach a max data transfer speed of 8/(32*70e-9) bit/s = 3.4 Mbit/s (am I correct?).
Providing the address only the first time, on the other side, I could transfer data about 4 time faster.

## Replies

### Reply 1 by becky, 2020-05-20

Hello,
<https://www.wiznet.io/wp-content/uploads/wiznethome/Chip/W3150A_Plus/Software/W3150A__DV_V109.zip>
Please refer to the 3150A + iolibrary code.

[![image](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/9/9be0bc470c6c7cc915740047734fa5fe9dfe6761.png) image744×679 26.8 KB](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/9/9be0bc470c6c7cc915740047734fa5fe9dfe6761.png)

Whenever you send 8-bit data, you must also transmit the opcode and address, and you need set high /SS and low again /SS.

![](https://avatars.discourse-cdn.com/v4/letter/m/a698b9/48.png) marco:

> I assume that the address will be automatically increased after the first 32 bit access (OPCODE(8bit)+ADDRESS(16 bit)+DATA(8 bit))

Address does not automatically increase.

![](https://avatars.discourse-cdn.com/v4/letter/m/a698b9/48.png) marco:

> If I need to perform a complete 32 bit access, according the min SCLK period reported in the datasheet (70 ns) I can reach a max data transfer speed of 8/(32*70e-9) bit/s = 3.4 Mbit/s (am I correct?).

No, 70ns is write cycle time in bus mode.
In addition, network performance should consider not only spi but also mii interface speed.
The W3150a + 's network performance is Max. 25Mbps.

### Reply 2 by marco, 2020-06-09 (in reply to reply 1)

I’m sorry but at page 63 there is the following table:

[![image](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/0/0f53827bb2f9943f9e1e5c0e36dd3005da069fa9.png) image730×685 50.7 KB](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/0/0f53827bb2f9943f9e1e5c0e36dd3005da069fa9.png)

At the sixth row there is the SCLK time minimum value, which is 70 ns. Is there an error in the datasheet or don’t I understand correctly?
If it is so, even if the max speed of the ethernet is 25Mb/s, the SPI access is the bottleneck of the comunication, isn’t it?

Thank you,
Marco

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Source: https://maker.wiznet.io/forum/13811