---
title: "CS deactivate during Parallel mode"
url: "https://maker.wiznet.io/forum/13758"
markdown_url: "https://maker.wiznet.io/forum/13758/md"
type: "Forum topic"
category: "Ethernet Chips"
author: "simon.peacock"
created: "2020-03-27T21:00:42+09:00"
last_activity: "2020-04-01T20:09:39+09:00"
language: "en"
views: 380
replies: 2
source: "WIZnet Makers forum (https://maker.wiznet.io/forum/)"
---

# CS deactivate during Parallel mode

## Question

Asked by simon.peacock on 2020-03-27 in Ethernet Chips.

We are looking at using the W6100 to replace an older Parallel Ethernet chip in an existing product.
After looking at the data sheet, I would like to know if CS can toggle high between bytes. In the diagrams, it always shows CS low for ADDRH, ADDRL, BS and data bytes which is unusual for processors since they can only keep CS low during device access. The CPU in this case is an older one too. But this is an existing product with a Renesas processor (M3087).

Simon

## Replies

### Reply 1 by irina, 2020-04-01

Wiznet chip is supposed to operate only when CS is low.
It can’t change to operate when CS is high.

### Reply 2 by simon.peacock, 2020-04-01 (in reply to reply 1)

but can there be a period of CS high between byte accesses?

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Source: https://maker.wiznet.io/forum/13758