---
title: "Time Between SPI Cycles"
url: "https://maker.wiznet.io/forum/13757"
markdown_url: "https://maker.wiznet.io/forum/13757/md"
type: "Forum topic"
category: "Ethernet Chips"
author: "MadScientist"
created: "2020-03-26T13:31:57+09:00"
last_activity: "2020-04-07T04:00:52+09:00"
language: "en"
views: 366
replies: 2
source: "WIZnet Makers forum (https://maker.wiznet.io/forum/)"
---

# Time Between SPI Cycles

## Question

Asked by MadScientist on 2020-03-26 in Ethernet Chips.

Hello, can anyone tell me if the W5100 has a specified minimum time between SPI cycles? More specifically, the minimum time between /CS assertions?

This is one parameter I’m unable to find in the device’s datasheet.

Thanks!

## Replies

### Reply 1 by irina, 2020-04-01

The minimum time or between /CS high and next /CS low is 32ns.
I think you can see in page 65 of datasheet :

[wiznet.io](https://www.wiznet.io/wp-content/uploads/wiznethome/Chip/W5100/Document/W5100_DS_V128E.pdf)

<https://www.wiznet.io/wp-content/uploads/wiznethome/Chip/W5100/Document/W5100_DS_V128E.pdf>

### [W5100_DS_V128E.pdf](https://www.wiznet.io/wp-content/uploads/wiznethome/Chip/W5100/Document/W5100_DS_V128E.pdf)

1390.79 KB

### Reply 2 by MadScientist, 2020-04-01 (in reply to reply 1)

My 1.1.6 version of the datasheet did not have this specified, and I would have been referring to the SPI section anyway.

Thank you for your response Irina!

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Source: https://maker.wiznet.io/forum/13757