--- title: "Problem in reading W5300 registers with Spartan6" url: "https://maker.wiznet.io/forum/13691" markdown_url: "https://maker.wiznet.io/forum/13691/md" type: "Forum topic" category: "Ethernet Chips" author: "tandis" created: "2020-02-09T08:45:55+09:00" last_activity: "2020-11-29T07:04:12+09:00" language: "en" views: 955 replies: 12 source: "WIZnet Makers forum (https://maker.wiznet.io/forum/)" --- # Problem in reading W5300 registers with Spartan6 ## Question Asked by tandis on 2020-02-09 in Ethernet Chips. Hi! I am using W5300 module and initialing it on TCP mode with Spartan6(FPGA). I can open the socket in TCP mode, and I also can establish it. When I send data to it and read the RX_FIFOR, I just cant read the number of data has been received . I create a loop for buffering data, but I can not read them. What is the problem? ## Replies ### Reply 1 by becky, 2020-02-10 Hello Did you have problem for establish. Could you please let me know how to get establish? [![image](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/a/add0fc68ab5655bca0e936faa5af1fc65df17b8d.png) image567×557 42.1 KB](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/a/add0fc68ab5655bca0e936faa5af1fc65df17b8d.png) please check if you follow this flow. ### Reply 2 by tandis, 2020-02-10 (in reply to reply 1) I have no problem with establish mode. I go to listen mode and when I click the connect button in the terminal , it goes to establish mode and SSR shows 0x17. For buffering data I am reading RX_FIFOR but I just get number of data that has been received , but in the other sequences when I read that register there is no data. ### Reply 3 by tandis, 2020-02-10 Yes, I can get ping and I can also connect to the device properly. But I have problem in reading registers. I can just read RX_FIFOR once and when I read it again there is no data in it, while a packet has been received ### Reply 4 by tandis, 2020-02-16 My main problem is the reading process. I can not read registers after eachother. I can read on register once or two different registers after each other. I do check Sn_RX_RSR value and it shows the right value, but then I can not read RX_FIFOR. I can just read RX_FIFOR0 once without reading other registers before that. ### Reply 5 by becky, 2020-02-19 (in reply to reply 4) [![image](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/d/de263b59d2902d07c4fff5c851dd38b504868fdd.png) image620×752 84.5 KB](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/d/de263b59d2902d07c4fff5c851dd38b504868fdd.png) Sorry, it is difficult to know the cause. I want to know if you followed that. Please check it. ### Reply 6 by tandis, 2020-02-19 Thanks for the reply! I do not use Sn_TX_FIFOR in my code at all. I just write in CR and read the result in Sn_SSR. When initializing, listening and establishing are done , I do the reading process of Sn_RX_FIFOR. I should mention that I also have problem in reading Sn_SSR sequentially ### Reply 7 by tandis, 2020-02-19 I have a seperate code of reading process( a reading function). I use that for reading any register. First I read Sn_SSR for initializing , listening and establishing.Then I go to Sn_RX_FIFOR reading process. I have problem in every step. I can just read just one of the registers not all of them sequentially. . ### Reply 8 by becky, 2020-02-19 [![image](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/d/d0712f415799255fc37124d4b732bd0600136f5e.png) image609×612 99.8 KB](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/d/d0712f415799255fc37124d4b732bd0600136f5e.png) Sorry I’m confused about Sn_RX_FIFOR and Sn_TX_FIFOR, but the same is true for Sn_RX_FIFOR . ### Reply 9 by tandis, 2020-02-19 Does it mean that I can not read Sn_RX_FIFOR0 and after a delay read Sn_RX_FIFOR1? Should I read them at the same time? Sorry I am confused ![:grimacing:](https://emoji.discourse-cdn.com/twitter/grimacing.png?v=12) ### Reply 10 by tandis, 2020-02-19 WiznetReadWrite_Process : process(s_CLK_20M) begin if rising_edge(s_CLK_20M) then ``` case s_Eth_RW_State is when c_Eth_RW_State_Idle => o_Eth_CS <= '1'; o_Eth_WR <= '1'; o_Eth_RD <= '1'; s_W_DATA_In_Des_Rdy <= '0'; s_W_DATA_Out_Des_Done <= '0'; if s_WriteTrig = '1' then s_W_RD_WRB <= '0'; o_Eth_CS <= '0'; s_W_ADDR <= s_W_ADDR_Des; s_W_DATA_Out <= s_W_DATA_Out_Des; s_Eth_RW_State <= c_Eth_RW_State_W1; elsif s_ReadTrig = '1' then s_W_RD_WRB <= '1'; s_W_ADDR <= s_W_ADDR_Des; o_Eth_RD <= '0'; o_Eth_CS <= '0'; s_Eth_RW_State <= c_Eth_RW_State_R1; end if; when c_Eth_RW_State_W1 => o_Eth_WR <= '0'; s_W_DATA_Out_Des_Done <= '1'; s_Eth_RW_State <= c_Eth_RW_State_Idle; when c_Eth_RW_State_R1 => s_W_DATA_In_Des <= s_W_DATA_In; s_W_DATA_In_Des_Rdy <= '1'; s_Eth_RW_State <=c_Eth_RW_State_Idle; when others => s_Eth_RW_State <= c_Eth_RW_State_Idle; end case; end if; end process; ``` This is my reading process And here is a part of main process which I start initializing in TCP mode after setting all socket registers and IP, MAC , PORT , … : ``` when c_Eth_Start_State => s_W_ADDR_Des <= c_WIZNET_START_ADDR(s_Index); s_W_DATA_Out_Des <= c_WIZNET_START_DATA(s_Index); s_WriteTrig <= '1'; if s_Index < c_WIZNET_START_ADDR_LENGTH-1 then s_Eth_Config_State <= c_Eth_Start_State2; else s_Eth_Config_State <= c_Eth_START_State_End; end if; s_Index <= s_Index + 1; when c_Eth_Start_State2 => if s_W_DATA_Out_Des_Done = '1' then s_Eth_Config_State <= c_Eth_START_State; end if; When c_Eth_START_State_End => s_Index<=0; s_Eth_Config_State <= c_Eth_check1_State; when c_Eth_check1_State=> s_W_ADDR_Des <="10"&x"09"; --S0_SSR s_ReadTrig <= '1'; if s_W_DATA_In_Des_Rdy='1' then mode<=s_W_DATA_In_Des; if mode=x"13" then s_Index <=0; s_LEDs<=x"00" & mode ; s_Eth_Config_State <=c_Eth_listen_State; else s_W_ADDR_Des <= c_WIZNET_START_ADDR(3); --CR1 s_W_DATA_Out_Des <= x"10"; --close s_WriteTrig <= '1'; if s_W_DATA_Out_Des_Done = '1' then s_Index <=0; s_Eth_Config_State <=c_Eth_Start_State; end if; end if; end if; when c_Eth_listen_State => s_W_ADDR_Des <= c_WIZNET_START_ADDR(3); --cr1 s_W_DATA_Out_Des <= x"02"; s_WriteTrig <= '1'; if s_W_DATA_Out_Des_Done='1' then s_Eth_Config_State <= c_Eth_delay_State; end if; when c_Eth_delay_State => counter<=counter+1; if (counter<4) then s_Eth_Config_State <= c_Eth_delay_State; else s_Eth_Config_State <= c_Eth_check_State; end if; When c_Eth_check_State => s_W_ADDR_Des <="10" & x"09"; --S0_SSR s_ReadTrig <= '1'; if s_W_DATA_In_Des_Rdy='1' then listen<=s_W_DATA_In_Des; if listen=x"14" then s_LEDs<=x"ff" & listen ; s_Index <=1; s_Eth_Config_State <= c_Eth_establish_State; else s_W_ADDR_Des <= c_WIZNET_START_ADDR(3); --CR1 s_W_DATA_Out_Des <= x"10"; --close s_WriteTrig <= '1'; if s_W_DATA_Out_Des_Done = '1' then s_Index <=0; s_Eth_Config_State <=c_Eth_Start_State; end if; end if; end if; when c_Eth_establish_State => s_W_ADDR_Des <=c_WIZNET_START_ADDR(4); --S0_SSR s_ReadTrig <= '1'; if s_W_DATA_In_Des_Rdy='1' then establish<=s_W_DATA_In_Des; if establish=x"17" then s_Index <=0; s_Eth_Config_State <= c_Eth_Receive_Process_State; else s_Index <=0; s_Eth_Config_State <=c_Eth_establish_State; end if; end if; when c_Eth_Receive_Process_State => s_W_ADDR_Des <= c_WIZNET_RXPACK_ADDR(1); --S0_RSR s_ReadTrig <= '1'; s_Index<= s_Index+1; if s_W_DATA_In_Des_Rdy='1' then if (s_Index counter<=counter+1; if (counter<4) then s_Eth_Config_State <= c_Eth_delay4_State; else s_Eth_Config_State <=c_Eth_cheksize_State; end if; when c_Eth_cheksize_State => rsr<=s_W_DATA_In_Des; if(rsr/=x"00") then s_Eth_Config_State <=c_Eth_receive1_State; else s_Eth_Config_State <=c_Eth_Receive_Process_State; end if; when c_Eth_receive1_State => s_W_ADDR_Des <= "10" & x"30"; s_ReadTrig <= '1'; if s_W_DATA_In_Des_Rdy='1' then data1<=s_W_DATA_In_Des; buff(step1)<=data; s_Eth_Config_State <=c_Eth_receive2_State; end if; when c_Eth_receive2_State => s_W_ADDR_Des <= "10" & x"31"; s_ReadTrig <= '1'; if s_W_DATA_In_Des_Rdy='1' then data2<=s_W_DATA_In_Des; buff(step2)<=data; s_Eth_Config_State <=c_Eth_Receive_Data_State; end if; when c_Eth_Receive_Data_State => s_LEDs<=x"00" & buff(step); step1<=step1+2; step2<=step2+2; if(step2>10) then step1<=0; step2<=1; s_Eth_Config_State <= c_Eth_REC_State; else s_Eth_Config_State <=c_Eth_delay5_State; end if; when c_Eth_delay5_State => counter<=counter+1; if (counter<4) then s_Eth_Config_State <= c_Eth_delay5_State; else s_Eth_Config_State <= c_Eth_receive1_State; end if; ``` ### Reply 11 by tandis, 2020-02-19 Thank you for the idea! I will change s_read_trig to 0 in other states and check the result. I will let you know ### Reply 12 by adityagour, 2020-11-29 Hi If you could interface w5300 with spartan-6 then kindly let me know. Did you interfaced using microblaze or did u used HDL for interfacing. --- Source: https://maker.wiznet.io/forum/13691