---
title: "Cannot receive ethernet packets"
url: "https://maker.wiznet.io/forum/13432"
markdown_url: "https://maker.wiznet.io/forum/13432/md"
type: "Forum topic"
category: "Ethernet Chips"
author: "gthind"
created: "2019-08-06T17:52:43+09:00"
last_activity: "2019-10-17T15:34:16+09:00"
language: "en"
views: 1032
replies: 6
source: "WIZnet Makers forum (https://maker.wiznet.io/forum/)"
---

# Cannot receive ethernet packets

## Question

Asked by gthind on 2019-08-06 in Ethernet Chips.

Hi,

I created a prototype ( a new PCB) with W5500 and Atmeg 2560. I have the SPI communication where I was able to set a mac and ip address. But somehow W5500 can’t receive any ethernet data passed by PLC. When I run code on a arduino ethernet shield with atmeg2560 I can receive the data assuming my firmware is correct. Here are few mistakes I

[![w5500](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/7/7dd38b7667230218113a6ff5f82143e3627896ea.png) w55001768×1368 46.4 KB](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/7/7dd38b7667230218113a6ff5f82143e3627896ea.png)

made in my prototype

1. Length of TX± not same (also with RX±)

2. Oscillator with lower gain than the recommended value of 6.983 (6.1243 < 6.983)

3. I left a ground plane under RJS-45.

But I do get the SPI connection correct with atmeg2560 , even with a lower gain oscillator. When I connect the ethernet jack I get the LINKLED as high, which is given in the datasheet as “LINK is not established”. Now, I’m making a production run but after correcting all those mistakes. I need to know if there is anything I’m doing wrong in Hardware before I make production pcb. I’ve attached my schematic.

Thanks,

G.T

## Replies

### Reply 1 by scott, 2019-08-07

Hi gthind

Your circuit is not expected to be problematic. Your problem may be to check the PCB Gerber file.

Can you upload the Gerber file here? The picture is fine, too.

Scott

### Reply 2 by gthind, 2019-08-08 (in reply to reply 1)

Hi Scott,

I just started working on the new layout, but as reference I’ve an R&D board file. Which I think is incorrect according to W5500 layout design rules.

[![Untitled](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/d/d0f7e23e8cdb579983ed6083a898e61cda6815d3.jpeg) Untitled1813×915 725 KB](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/d/d0f7e23e8cdb579983ed6083a898e61cda6815d3.jpeg)

Thanks, gthind

### Reply 3 by scott, 2019-08-13

I think it’s very bad.

Please refer to the URL below.

<http://wizwiki.net/wiki/doku.php?id=design_guide:hardware:start>

Thank you

### Reply 4 by gthind, 2019-10-16

Hi Scott,

I did the PCB layout for that board again with W5500 IC. I kept the tx+ tx- traces distance 10mil.

[![W5500](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/b/ba6d3c53188761b26722f553b5ab952004e4da53.png) W55001233×715 143 KB](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/b/ba6d3c53188761b26722f553b5ab952004e4da53.png)

### Reply 5 by scott, 2019-10-17

Dear gthind

I think you designed it well. What layer is this PCB?

Do you have any questions?

thank you.

### Reply 6 by gthind, 2019-10-17

This is 4 layer PCB with area underneath RJ45 completely isolated. Thanks, GT

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Source: https://maker.wiznet.io/forum/13432