--- title: "Problem with w5100 module Drive using Spartan-6" url: "https://maker.wiznet.io/forum/13162" markdown_url: "https://maker.wiznet.io/forum/13162/md" type: "Forum topic" category: "Ethernet Chips" author: "javadhabibi" created: "2019-01-08T10:29:52+09:00" last_activity: "2019-01-14T11:52:14+09:00" language: "en" views: 932 replies: 20 source: "WIZnet Makers forum (https://maker.wiznet.io/forum/)" --- # Problem with w5100 module Drive using Spartan-6 ## Question Asked by javadhabibi on 2019-01-08 in Ethernet Chips. Hi, I have a FPGA (spartan-6) board with a [W5100 module](http://shieldlist.org/arduino/ethernet-v5) that connected to main FPGA board. I want to ping module through CMD. The default ping IP(192.168.1.100) works fine. But when I want to change the default IP to 192.168.1.113 it seems the command doesn’t received correctly in wiznet module. Here is my simulation. what is wrong? [![SET_IP_Simulation](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/a/a24e25b044531a3d0caf23b1951d1f961b874ba4.png) SET_IP_Simulation727×145 5.95 KB](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/a/a24e25b044531a3d0caf23b1951d1f961b874ba4.png) [SET_IP_Simulation.pdf](https://maker.wiznet.io/forum/legacyFile.asp?path=oCOdZ5UM28uKuCknAkuiKRVCoix.pdf) (1.6 KB) - change the .pdf in the name of file to .wcfg to see the full simulation in ISIM.(this format is not authorized for uploading) ## Replies ### Reply 1 by irina, 2019-01-09 Hi, First, I can’t show your pdf file. The file is corrupted and cannot be opened. If you change ip addr from 192.168.1.100 to 192.168.1.113, you write the data('d113) in the register address(0x12) though MOSI. I will be waiting to hear from you. ('d![KakaoTalk_20190109_090324472](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/c/c77834afbfe2ca691f31d34c8ef9068984f5c94e.jpeg) Thanks, Best regards, irina ### Reply 2 by Eugeny, 2019-01-09 ![](https://avatars.discourse-cdn.com/v4/letter/j/59ef9b/48.png) javadhabibi: > [![SET_IP_Simulation](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/a/a24e25b044531a3d0caf23b1951d1f961b874ba4.png) SET_IP_Simulation.PNG727×145 5.95 KB](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/a/a24e25b044531a3d0caf23b1951d1f961b874ba4.png) You send 192 to register 0x0F here. Do you change other 4 registers as [@irina_kim](https://maker.wiznet.io/u/irina_kim) said? ### Reply 3 by javadhabibi, 2019-01-09 the other 3 bytes are set just like the first. [![SET_IP_Simulation_countinus_3](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/4/4c97e476447f0fa79a99a7cd6401cccd87b4b0c3.png) SET_IP_Simulation_countinus_3913×172 6.45 KB](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/4/4c97e476447f0fa79a99a7cd6401cccd87b4b0c3.png) - If these are important factors: 1- I had connected the module directly to my laptop. 2- Changing IP and the Pinging is my first work with module. I hadn’t change any setting, registers,etc. ### Reply 4 by Eugeny, 2019-01-09 (in reply to reply 3) Please show real state of MISO when you write new IP address. As you have W5100 configured the first place I guess it is a proof that SPI communication works properly and what you show in simulation reaches W5100 registers, right? ### Reply 5 by javadhabibi, 2019-01-09 I am setting my FPGA’s output data on “MOSI” pin. Is it wrong? ### Reply 6 by Eugeny, 2019-01-09 ![](https://avatars.discourse-cdn.com/v4/letter/j/59ef9b/48.png) javadhabibi: > I am setting my FPGA’s output data on “MOSI” pin. Is it wrong? Why do you think so? I am asking for output of MISO pin of W5100. During write cycle is must output specific values to prove that your write is being accepted by the chip. ### Reply 7 by javadhabibi, 2019-01-09 The MISO is Zero during write operation. is it True? ### Reply 8 by Eugeny, 2019-01-09 (in reply to reply 7) No, please read 6.3.3 of the datasheet, and look at the picture in there. ### Reply 9 by javadhabibi, 2019-01-10 After some correction in board’s connections, the MISO feedback is not reasonable yet. Once it is True and Once Not. what is the probably cause? In the Picture, from top to down are : SCK, MOSI, MISO, SS True MISO: [![1_True_a](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/7/7da9e1e9023d4a2849cf63d98951454d9db0b0f7.jpeg) 1_True_a4000×2250 964 KB](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/7/7da9e1e9023d4a2849cf63d98951454d9db0b0f7.jpeg) - Power: 4.5 V *SCK Frequency: 500 Khz - SCK and MOSI Voltage: 0 - 3.3V ### Reply 10 by javadhabibi, 2019-01-10 False MISO: [![2_false_b](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/d/d2f471908c636af5ec27f4fbb295f98c9b1b2123.jpeg) 2_false_b4000×2250 928 KB](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/d/d2f471908c636af5ec27f4fbb295f98c9b1b2123.jpeg) ### Reply 11 by Eugeny, 2019-01-10 (in reply to reply 10) ![](https://avatars.discourse-cdn.com/v4/letter/j/59ef9b/48.png) javadhabibi: > False MISO: The only possible cause comes to my mind is that one of previous SPI cycles did not finish with number of active clocks (when SS is low) in multiple of 8. ### Reply 12 by javadhabibi, 2019-01-10 I check the active clk number in each period and it is exactly 32. should i check the W5100 to be free (Not busy, For example because of Auto ARP, ICMP, etc)? ### Reply 13 by Eugeny, 2019-01-10 (in reply to reply 12) ![](https://avatars.discourse-cdn.com/v4/letter/j/59ef9b/48.png) javadhabibi: > I check the active clk number in each period and it is exactly 32. Then suggestion: before driving SS low, perform 8 spare clock pulses with SS high. In general you have something wrong with your SPI implementation, the question is what is wrong and how to fix it. ### Reply 14 by javadhabibi, 2019-01-10 Problem Solved. The SPI Mode 3 is deleted on Ver. 1.1.8 Mar. 4, 2009. I Used Ver. 1.1.6 and that’s caused the problem. because in Low-period of SS, I have 32 Rising Edge of SCK, but Just 31 falling edge of it. Thanks Eugeny. It is Precisely what you said about active clocks. Here the corrected wave form. [![True_SS](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/9/9da4ede66c131c9f6ee4d30d57aa0880865ffc04.png) True_SS873×77 1.87 KB](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/9/9da4ede66c131c9f6ee4d30d57aa0880865ffc04.png) ### Reply 15 by irina, 2019-01-11 (in reply to reply 14) I ’ m glad it all worked out for you , Feel free to ask any questions. ### Reply 16 by javadhabibi, 2019-01-12 EXCUSE ME, I am hurried up. the problem not solved! please help me with this amazing problem. I have connected my module to my board with ICSP port(MISO/SCK/RST/+5/MOSI/GND) + a wire for SS(pin 10 of board header). But the MISO feedback is precisely alternate(once true and once not). I am so confussed. [![Ethernet_shield_lq](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/1/144fbb749794a1f6010d6fca620f4beba9ff1a7b.jpeg) Ethernet_shield_lq1412×996 314 KB](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/1/144fbb749794a1f6010d6fca620f4beba9ff1a7b.jpeg) ### Reply 17 by javadhabibi, 2019-01-12 [![SPI_Signals](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/b/b16b50d7f4d8c53e2d3f3c087426d808938f15c5.jpeg) SPI_Signals1280×960 196 KB](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/b/b16b50d7f4d8c53e2d3f3c087426d808938f15c5.jpeg) ### Reply 18 by irina, 2019-01-14 (in reply to reply 17) ![](https://avatars.discourse-cdn.com/v4/letter/j/59ef9b/48.png) javadhabibi: > ternate(once true and once not). > I am so confussed. I saw your capture wave. I don’t find the SCLK waveform in your wave file. The minimum guaranteed speed of the SCLK is 33.3 MHz which was tested and measured with the stable waveform. You have to use the SPI CLOCK than less 33.3MHz, is it right? about your wareform 1,MOSI 2.MISO 3. CSn ### Reply 19 by javadhabibi, 2019-01-14 Yes the clock is right. After many tries on different probable causes, i found that i should wait at least 10 ms after reset w5100. By changing it, the MISO response is true. Ping and TCP connection is ok. But i have data receive problem that i would post it in a new topic. Thanks for your good support. ### Reply 20 by Eugeny, 2019-01-14 ![](https://avatars.discourse-cdn.com/v4/letter/j/59ef9b/48.png) javadhabibi: > i found that i should wait at least 10 ms after reset w5100 We assume you read datasheet before making a design. Dataheet says on page 65 that reset to PLOCK is exactly 10 ms. You also must wait until bit 7 of MR will clear to 0 after power up or reset. --- Source: https://maker.wiznet.io/forum/13162