---
title: "how W5500 memory map arranged?"
url: "https://maker.wiznet.io/forum/13100"
markdown_url: "https://maker.wiznet.io/forum/13100/md"
type: "Forum topic"
category: "Ethernet Chips"
author: "alecksis"
created: "2018-11-01T17:08:14+09:00"
last_activity: "2018-11-02T00:34:48+09:00"
language: "en"
views: 919
replies: 4
source: "WIZnet Makers forum (https://maker.wiznet.io/forum/)"
---

# how W5500 memory map arranged?

## Question

Asked by alecksis on 2018-11-01 in Ethernet Chips.

hi, dear developers!
i can’t understand how arranged memory in W5500.
there is code from official library **W5500.c**

```
   void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint16_t len)
   {
   uint16_t ptr = 0;
   uint32_t addrsel = 0;

   if(len == 0)  return;
   ptr = getSn_TX_WR(sn);
   //M20140501 : implict type casting -> explict type casting
   //addrsel = (ptr << 8) + (WIZCHIP_TXBUF_BLOCK(sn) << 3);
   addrsel = ((uint32_t)ptr << 8) + (WIZCHIP_TXBUF_BLOCK(sn) << 3);
   //
   WIZCHIP_WRITE_BUF(addrsel,wizdata, len);
   
   ptr += len;
   setSn_TX_WR(sn,ptr);
   }
```

I calculate addrsel for all SOCKETs. It is

socket0 H00224:L00016
socket1 H00224 L00048
socket2 H00224 L00080
socket3 H00224 L00112
socket4 H00224 L00144
socket5 H00224 L00176
socket6 H00224 L00208
i don’t understand, why behind sockets only (48-16=32) (80-48=32) (112-80=32) etc ?
and buffer for TX must be 2kB.

## Replies

### Reply 1 by alecksis, 2018-11-01

can anybody explain, how memory map work in w5500. with picture please. i try to understand memory arrange with library code. but it so difficult , it’s impossible !

### Reply 2 by crees, 2018-11-01 (in reply to reply 1)

Are you trying to increase buffer on TX / RX ? If so look at this github link. This shows how to use more sockets to increase RX TX Buffer.

![](https://github.githubassets.com/favicons/favicon.svg) [GitHub](https://github.com/sstaub/Ethernet3)

![](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/f/fb4bf073b9216e5ec43445cc86450bc2ae0105f4.png)

### [GitHub - sstaub/Ethernet3: Ethernet library for Arduino and Ethernetshield2 /...](https://github.com/sstaub/Ethernet3)

Ethernet library for Arduino and Ethernetshield2 / WIZ550io / WIZ850io / USR-ES1 with Wiznet W5500 chip - GitHub - sstaub/Ethernet3: Ethernet library for Arduino and Ethernetshield2 / WIZ550io / WI...

Pay Attention to Socket RAM Size.

### Reply 3 by vanvught, 2018-11-01 (in reply to reply 1)

Please see the datasheet, the memory layout is explained in section 3 Register and Memory Organization

Arjan

### Reply 4 by jameskim, 2018-11-02

Hello,

The address calculation equation is to make “address and control phase” in SPI Frame of W5500.
The Address and Control Phase consists of two address bytes and one control byte.
So, ptr was shifted left by one byte

```
((uint32_t)ptr << 8)
```

and block select bits

are shifted by 3 bits

```
(WIZCHIP_TXBUF_BLOCK(sn) << 3)
```

to make the control phase byte.
In WIZCHIP_WRITE_BUF, Control Phase will be processed more.

[![Screenshot_2018-11-02%20iEthernet%20W5500%20Datasheet%20kr%20-%20products%20w5500%20w5500_ds_v108e%20pdf](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/b/b5f6c737b63ba4c5fbc68ce5484701e83e183d1a.png) Screenshot_2018-11-02%20iEthernet%20W5500%20Datasheet%20kr%20-%20products%20w5500%20w5500_ds_v108e%20pdf787×259 11.4 KB](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/b/b5f6c737b63ba4c5fbc68ce5484701e83e183d1a.png)

Thank you.
BR,

James.

---

Source: https://maker.wiznet.io/forum/13100