---
title: "Using FPGA, cannot OPEN socket"
url: "https://maker.wiznet.io/forum/12868"
markdown_url: "https://maker.wiznet.io/forum/12868/md"
type: "Forum topic"
category: "IO Modules"
author: "keegi"
created: "2018-04-21T15:35:23+09:00"
last_activity: "2021-05-03T14:09:06+09:00"
language: "en"
views: 816
replies: 1
source: "WIZnet Makers forum (https://maker.wiznet.io/forum/)"
---

# Using FPGA, cannot OPEN socket

## Question

Asked by keegi on 2018-04-21 in IO Modules.

Hi, I am using WIZ811MJ, attached to FPGA in parallel mode. The initialization looks good, and module is replying to ping. However, whenever I’m trying to open a socket (UDP or TCP), there is no reaction to writing to Sx_CR, it does not get cleared and Sx_SR remains at 0.

I have checked quite few times the datasheet, but obviously I am still missing something.

Here’s the output from signal analyzer:

[![w51-analyze](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/d/d833882e5c440e58f81a4bb5f452a25c38194edd.png) w51-analyze1833×344 71.9 KB](https://maker.wiznet.io/forum_uploads/wiznet/original/2X/d/d833882e5c440e58f81a4bb5f452a25c38194edd.png)

Would be grateful for any pointers.

## Replies

### Reply 1 by keegi, 2018-04-25

Okay, the problem was in hardware - two of the address lines were swapped so that instead of writing to the command register it ended up in the buffer memory. Now the socket opens fine.

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Source: https://maker.wiznet.io/forum/12868