---
title: "W5500 reset timing - Do I need to wait after LOW pulse?"
url: "https://maker.wiznet.io/forum/12136"
markdown_url: "https://maker.wiznet.io/forum/12136/md"
type: "Forum topic"
category: "Ethernet Chips"
author: "sofakng"
created: "2017-02-07T19:58:13+09:00"
last_activity: "2017-05-04T08:39:46+09:00"
language: "en"
views: 1397
replies: 3
source: "WIZnet Makers forum (https://maker.wiznet.io/forum/)"
---

# W5500 reset timing - Do I need to wait after LOW pulse?

## Question

Asked by sofakng on 2017-02-07 in Ethernet Chips.

I’m reading the datasheet for the W5500 chip and it sounds like a reset is not required but is recommended?

Also, which is the correct reset procedure?

```
RSTn -> Low
Wait 500us + 50ms (total = 50.5ms)
RSTn -> High
```

…or

```
RSTn -> Low
Wait 500us
RSTn -> High
Wait 50ms
```

## Replies

### Reply 1 by Eugeny, 2017-02-10

Where did you find 50 ms? 5.5.1 “reset timing” states that you should have reset signal active for at least Trc=500 us (but if you wish you can have it 50 ms), and then you have to wait for at least Tpl=1 ms until PLL stabilizes.

### Reply 2 by sofakng, 2017-02-11

Thanks for the reply.

I was referring to this comment:

[quote]User need to wait for 50ms after this pin is changed to HIGH to communicate with WIZ850io. (Refer to 5. Timing Diagram)[/quote] as found here: [wizwiki.net/wiki/doku.php?id=pro … 50io:start](http://wizwiki.net/wiki/doku.php?id=products:wiz850io:start)

### Reply 3 by Eugeny, 2017-02-11

If you would look into datasheet for the W5500 chip, you will see than TPL is 1 ms, not 50 ms. This is a question to the people who write datasheets and design chips.
Anyway, ss soon as you use this specific module, to be 100% correct from spec point of view comply to these 50 ms.

This one is correct:

`RSTn -> Low Wait 500us RSTn -> High Wait 50ms (use chip)`

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Source: https://maker.wiznet.io/forum/12136