---
title: "Disable socket buffer. Increase available SRAM"
url: "https://maker.wiznet.io/forum/11796"
markdown_url: "https://maker.wiznet.io/forum/11796/md"
type: "Forum topic"
category: "MCU & Boards"
author: "pherig"
created: "2016-04-14T17:27:00+09:00"
last_activity: "2024-12-30T19:05:05+09:00"
language: "en"
views: 1388
replies: 8
source: "WIZnet Makers forum (https://maker.wiznet.io/forum/)"
---

# Disable socket buffer. Increase available SRAM

## Question

Asked by pherig on 2016-04-14 in MCU & Boards.

Dear,

I am working with the W7500P IOP and I am trying to allow my program to use 48k of SRAM based on the information provided at Wiznet’s website: SRAM: 16KB to 48 KB ( Min 16KB available if 32KB socket buffer is used, Max 48KB available if no socket buffer is used)

However, I am having trouble to disable the socket buffer.

Can someone please assist me in this matter?

Best regards,
Pedro

## Replies

### Reply 1 by lawrence, 2016-04-20

Hello, pherig

As you know 32KB sram assigned in 8 ch socket and we offer users the registers to control the socket buffer size.

In Reference Sheet, there are Sn_TXBUF_SIZE and Sn_RXBUF_SIZE registers.

So, may you set all sockets 0Byte then you will use MAX 48KB.

Thank you

lawrence

### Reply 2 by pherig, 2016-05-18

Thanks for answering lawrence and for the information shared.

I have developed a function that allocates memory until malloc answer null in order to measure how much memory is still available and even though I change Sn_TXBUF_SIZE and Sn_RXBUF_SIZE registers, the result is always the same (~8KB). Is this happening because the memories are not a single-memory of 48KB and the heap cannot use two different memories at the same time?

Do I have to change the Read/Write Memory Areas at Keil (memory remap) in order to be able to use the extra memory released from the sockets?

I assume there are two SRAMs: 16KB and 32KB. Is this correct? If so, can I have 3 sockets enabled (3 x [2KB + 2KB] = 12KB) and assign the remaining 20KB of the extra memory for Heap?

Thanks again.

Regards,
Pedro

### Reply 3 by pherig, 2016-05-20

Adding more details:

I have been able to change the scatter file and the .s file in order to change the memory map, but I don’t know what changes should be done.
My goal is to have a single ram with 48Kb but in the worst scenario I could work with segmented rams if the stack is not in the main one.

Based in the documentation, I tried to add a new ram and move the initial_stacker_pointer to an address in the new ram but I didn’t manage to understand what should be this new address. I believe this information is in the W7500P Reference Manual Version 1.0.3 ( Figure 5. Register & Memory Organization pg 43) but I didn’t understand it. Can some one please support me?

### Reply 4 by 8milan8, 2016-10-17

[quote=“pherig”]Adding more details:

I have been able to change the scatter file and the .s file in order to change the memory map, but I don’t know what changes should be done.
My goal is to have a single ram with 48Kb but in the worst scenario I could work with segmented rams if the stack is not in the main one.

Based in the documentation, I tried to add a new ram and move the initial_stacker_pointer to an address in the new ram but I didn’t manage to understand what should be this new address. I believe this information is in the W7500P Reference Manual Version 1.0.3 ( Figure 5. Register & Memory Organization pg 43) but I didn’t understand it. Can some one please support me?[/quote]

Read reference manual section 7.4. But after reading, I think that the parameter 48 KB SRAM are crap. You can’t simple use this memory. The first problem is that the memory is separated from the main SRAM. So it could be used only for the heap and the limited use. But i not tried it.

I wanted to use TLS, but now I know that there is only 16 KB of SRAM, so it will not work. I wish they did next generation of this chip that will repair the problems (RTC and add main SRAM memory).

### Reply 5 by lawrence, 2017-07-20 (in reply to reply 3)

Hello, pherig

I think one of ways to use is user have to set the 32K memory(socket) as SRAM in IDE.

In KEIL, there is the configuration tool for setting SRAM, more than one.

Because it is separated from main SRAM.

### Reply 6 by Bagler, 2017-08-23

Lawrence, thank you for your answers,
Can you please give some more detailed explanations of reference manual Figure 5, section 7.4. What address should be used to access Socket 7 TX buffer for instance?
Thanks in advance!

### Reply 7 by pherig, 2017-09-05 (in reply to reply 6)

I did several tests and the only one that worked for me was the following linker settings:

> LR_IROM1 0x00000000 0x00020000 { ; load region size_region
> ER_IROM1 0x00000000 0x00020000 { ; load address = execution address
> *.o (RESET, +First)
> *(InRoot$$Sections)
> .ANY (+RO)
> }
> RW_IRAM2 0x461FF800 0x800 {
> main.o (+ZI +RW)
> }
> RW_IRAM1 0x20000000 0x00004000 {
> .ANY (+RW +ZI)
> }
> }

But this settings only increase 2kb in the available RAM and I had to reduce the maximum number of sockets available.

Hope this helps someone in the future.

### Reply 8 by barcaluti, 2024-12-30 (in reply to reply 6)

Hi everybody

Thanks for sharing your thoughts! I know it´s a bit old, but just in case...

Didn´t you have problems using this TOE RAM such as some memory areas (in TOE RAM section) overwritting other areas (in TOE RAM section, but different socket)?

I´m afraid I´m not understanding something. In my case, I defined two memory sections:

SOCKET7_TX_RAM: origin 0x461EF800, length 2K

SOCKET6_TX_RAM: origin 0x461AF800, length 2K

I´m placing some variables in SOCKET7_TX_RAM and some others in SOCKET6_TX_RAM. While debugging, I can see that writing variables in SOCKET7_TX_RAM overwrites variables in SOCKET6_TX_RAM (those placed at the same offset with respect to the origin of the section, that is, to the origin of the TX buffer).

Did you experience something similar?

Thanks in advance.

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Source: https://maker.wiznet.io/forum/11796