---
title: "LPC_W5500_TCPStream"
url: "https://maker.wiznet.io/Grace_Koo/projects/lpc-w5500-tcpstream/"
markdown_url: "https://maker.wiznet.io/Grace_Koo/projects/lpc-w5500-tcpstream/md"
type: "UCC: User Created Content"
author: "Grace"
author_url: "https://maker.wiznet.io/Grace_Koo/"
original_author: "Grace Koo"
original_url: "https://github.com/mohammadrezahosseini99/LPC_W5500_TCPStream.git"
published: "2025-12-09"
language: "en"
hardware: ["WIZnet W5500"]
likes: 0
views: 297
comments: 0
source: "WIZnet Makers (https://maker.wiznet.io/)"
---

# LPC_W5500_TCPStream

> First-ever W5500 driver for NXP LPC54114 dual-core MCU. Custom non-blocking implementation filling the gap in industrial Ethernet solutions.

Original author: Grace Koo (source: https://github.com/mohammadrezahosseini99/LPC_W5500_TCPStream.git)

## Components

- **WIZnet W5500** x 1 ([docs](https://docs.wiznet.io/Product/Chip/Ethernet/W5500))

WIZnet parts: W5500 ([Datasheet](https://docs.wiznet.io/Product/Chip/Ethernet/W5500/datasheet?utm_source=maker&utm_medium=project&utm_campaign=w5500), [product hub](https://maker.wiznet.io/products/w5500/))

## Documents and links

- [GitHub:LPC_W5500_TCPStream](https://github.com/mohammadrezahosseini99/LPC_W5500_TCPStream.git) (code)

## Article

** Cover Image in this article were generated by Gemini.*

## Overview

WIZnet is excited to share a groundbreaking reference implementation: the first W5500 integration with NXP's LPC54114 dual-core microcontroller. This project fills a critical gap in the embedded Ethernet ecosystem, providing NXP developers with a proven path to add robust networking capabilities to their designs.

## Why This Matters

**Market Gap Analysis**

Our GitHub research revealed a striking pattern:

- LPC + W5500 projects: 0 results

- LPC + ENC28J60: Limited to legacy ARM7 designs

- LPC1768 projects: Rely on built-in Ethernet MAC

This is the first production-ready W5500 driver for the NXP LPC54xxx series.

***Technical Differentiation***

| Feature | This Project | Typical Alternatives |
| --- | --- | --- |
| Platform | LPC54114 (Dual Cortex-M4+M0+) | LPC1768 (built-in MAC) or ENC28J60 |
| Driver Architecture | Custom non-blocking SPI | Generic blocking libraries |
| Performance | 60MHz SPI, hardware TCP/IP | 10Mbps (ENC28J60) |
| Development | MCUXpresso IDE native | Mixed toolchains |

## Getting Started

1. Hardware Setup: Connect W5500 module to LPC54114 via SPI6

2. Configuration: Adjust IP settings in `W5500_config.h`

3. Build: Import project into MCUXpresso IDE

4. Deploy: Flash and connect via Ethernet

Detailed documentation available in `/doc` directory.

- **Pin Mapping Table**

| LPC54114 Pin | Function | W5500 Pin | Pin Number | Notes |
| --- | --- | --- | --- | --- |
| **PIO0_5** | SPI6 MOSI | MOSI | 39 | Master Out Slave In |
| **PIO0_6** | SPI6 MISO | MISO | 40 | Master In Slave Out |
| **PIO0_7** | SPI6 SCK | SCLK | 41 | SPI Clock (60MHz) |
| **PIO1_11** | SPI6 SSEL1 | SCSn | 42 | Chip Select (Active Low) |
| **PIO0_2** | GPIO Input | INTn | 36 | Link Status / Interrupt (Optional) |
| **3.3V** | Power | VDD | - | 3.3V Power Supply |
| **GND** | Ground | GND | - | Ground |

- **Additional W5500 Connections**

| W5500 Pin | Connection | Notes |
| --- | --- | --- |
| **RSTn** | 3.3V (Pull-up 10kΩ) | Hardware reset (Active Low) |
| **PMODE[2:0]** | All to GND or VDD | Configure PHY mode (see W5500 datasheet) |
| **RJ45 Interface** | Ethernet Jack with magnetics | Use integrated magnetics module |

## Key Features

**1. Custom W5500 Driver Development**

Unlike most W5500 implementations that use WIZnet's standard ioLibrary, this project features a platform-optimized custom driver specifically designed for NXP's architecture:

```c
// Non-blocking SPI architecture with callback mechanism
__DATA(SRAM2) W5500_t myW5500;  // Optimized memory placement

static void w5500_spi_Callback(SPI_Type *base, spi_master_handle_t *handle,
                                status_t status, void *userData) {
    W5500_spiCallBack(&myW5500);
}
```

Benefits:

- Seamless integration with NXP HAL drivers

- Non-blocking operation for real-time systems

- Efficient memory management using SRAM2

- State machine-based implementation

**2. Dual-Core Ready Architecture**

The LPC54114's Cortex-M4 + M0+ configuration opens unique possibilities:

- M4 core: Network communication + main application logic

- M0+ core: Sensor management, safety functions, or auxiliary tasks

**3. Industrial-Grade Reliability**

This combination brings together:

- NXP LPC54114: Long-term availability, extended temperature range, safety certifications

- W5500: Proven hardware TCP/IP stack with 8 independent sockets

**4. High-Speed SPI Interface**

```c
userConfig.baudRate_Bps = 60000000U;  // 60MHz SPI clock
```

Maximum throughput with W5500's hardware-accelerated protocol stack.

## Architecture Highlights

**Hardware TCP/IP Offloading**

W5500 handles the entire network stack, freeing the MCU for application tasks:

- No software TCP/IP stack overhead

- Reduced RAM footprint

- Deterministic timing for industrial applications

**Efficient Resource Usage**

```c
#define MAX_REC    200
// Optimized buffer management
uint8_t recDataBack[MAX_REC + 10] = {'R','e','c','e','i','v','e','d',':',' '};
```

**Real-Time Echo Server Implementation**

Demonstrates practical networking patterns:

- TCP server with automatic reconnection

- Non-blocking receive with timeout

- Periodic heartbeat messages

- Echo functionality with prefix

## Target Applications

This reference design is ideal for:

**Industrial Automation**

- Factory floor controllers

- PLC connectivity

- Remote monitoring systems

- Machine-to-machine (M2M) communication

**Building Automation**

- HVAC control systems

- Access control

- Energy management

- Sensor aggregation nodes

**Medical Devices**

- Patient monitoring equipment

- Laboratory instruments

- Data logging systems

**General IoT**

- Edge gateways

- Data acquisition systems

- Remote control interfaces

## Technical Specifications

Hardware:

![](https://www.nxp.com/assets/images/en/chip-images/sot314-2_3d.gif?imwidth=2048)

- MCU: NXP LPC54114 (Cortex-M4F @ 150MHz + M0+ @ 100MHz)

- Ethernet: WIZnet W5500 (Hardware TCP/IP)

- Interface: SPI @ 60MHz

- Memory: 256KB Flash, 192KB RAM

Software:

- IDE: MCUXpresso

- Framework: NXP SDK with CMSIS

- Debug: J-Link support

- Driver: Custom W5500 implementation (Version 1.2)

Performance:

- TCP throughput: Up to 25Mbps (limited by SPI bandwidth)

- Latency: Sub-millisecond response time

- Connections: Supports up to 8 simultaneous TCP/UDP sockets

## What's Included

```c
├── Custom W5500 Driver (v1.2)
│   ├── W5500.c/h - Core driver implementation
│   └── W5500_config.h - Configuration parameters
├── Complete HAL Integration
│   ├── SPI, GPIO, UART drivers
│   └── Clock and power management
├── TCP Echo Server Example
│   └── Production-ready application template
└── MCUXpresso Project Files
    └── Ready to build and debug
```

## Expanding the W5500 Ecosystem

At WIZnet, we're committed to supporting diverse microcontroller platforms. This project demonstrates W5500's versatility beyond the traditional STM32 ecosystem, now bringing proven Ethernet connectivity to the NXP LPC architecture.

#### Credits

Driver Development: Mohammadreza Hosseini
Platform: NXP LPC54114
Ethernet Controller: WIZnet W5500

#### Resources

- [W5500 Datasheet](https://docs.wiznet.io/Product/Chip/Ethernet/W5500)

- [LPC54114 Product Page](https://www.nxp.com/part/LPC54114J256BD64)

- [MCUXpresso IDE](https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/mcuxpresso-integrated-development-environment-ide:MCUXpresso-IDE)

- [WIZnet Forum](https://maker.wiznet.io/)

#### Community & Support

We encourage developers to:

- Share your LPC + W5500 implementations

- Report issues and contribute improvements

- Join the discussion on WIZnet forums

This project proves that W5500 is the versatile Ethernet solution for any ARM platform.

---

## Why Choose W5500 for Your Next NXP Design?

- Hardware TCP/IP: Reduce firmware complexity

- Proven Reliability: Millions deployed worldwide

- Easy Integration: SPI interface, minimal external components

- Cost-Effective: Complete networking for under $3

- Multi-Platform: Now proven on NXP LPC architecture

---

Source: https://maker.wiznet.io/Grace_Koo/projects/lpc-w5500-tcpstream/