--- title: "ESP32S3_W5500_SOES" url: "https://maker.wiznet.io/Grace_Koo/projects/esp32s3-w5500-soes/" markdown_url: "https://maker.wiznet.io/Grace_Koo/projects/esp32s3-w5500-soes/md" type: "UCC: User Created Content" author: "egerobotics" author_url: "https://github.com/egerobotics/ESP32S3_W5500_SOES" editor: "WIZnet" editor_url: "https://maker.wiznet.io/" original_author: "egerobotics" original_url: "https://github.com/egerobotics/ESP32S3_W5500_SOES" published: "2026-03-26" language: "en" likes: 0 views: 573 comments: 0 source: "WIZnet Makers (https://maker.wiznet.io/)" --- # ESP32S3_W5500_SOES > A software EtherCAT slave built with ESP32-S3 and WIZnet W5500. No dedicated ESC chip needed — raw frames processed in software via SOES stack. Original author: egerobotics (source: https://github.com/egerobotics/ESP32S3_W5500_SOES) ## Article ## Software EtherCAT Slave Built with ESP32-S3 + W5500 #### An open-source project that implements a fully functional EtherCAT slave using only a general-purpose MCU and an SPI Ethernet chip — no dedicated ESC hardware required. --- | Item | Details | | --- | --- | | **Author** | egerobotics | | **Target Technology** | Software EtherCAT Slave Controller (ESC) emulation | | **Hardware** | ESP32-S3 + WIZnet W5500 (SPI Ethernet) | | **EtherCAT Stack** | SOES (Simple Open EtherCAT Slave, GPLv2) | | **Build Environment** | ESP-IDF v5.3.x, CMake | | **Compatible Masters** | TwinCAT 3 and other standard EtherCAT masters | | **GitHub** | [egerobotics/ESP32S3_W5500_SOES](https://github.com/egerobotics/ESP32S3_W5500_SOES) | --- ## What Is This Project? **EtherCAT** is an industrial communication protocol widely used in factory automation. Robot arms, servo motors, and I/O modules all use EtherCAT to communicate with a master controller. The catch is that building an EtherCAT slave device normally requires a **dedicated hardware chip called an ESC (EtherCAT Slave Controller)**. Without it, EtherCAT communication simply isn't possible — at least, not in the conventional approach. This project replaces that dedicated chip entirely **in software**. By combining an ESP32-S3 microcontroller with a WIZnet W5500 Ethernet chip, it implements a fully functional EtherCAT slave — no ASIC required. The system has been verified to work with TwinCAT 3, one of the industry-standard EtherCAT master platforms, including device discovery and I/O control. > 💡 **In one sentence:** An open-source project that implements a software EtherCAT slave using only an ESP32-S3 + W5500 — no expensive dedicated chip needed. --- ## 1. Background EtherCAT is a real-time Ethernet protocol used in industrial automation. Devices such as servo drives, distributed I/O modules, and motion controllers that need to operate as EtherCAT slaves typically require a **dedicated EtherCAT Slave Controller (ESC) ASIC** — such as Beckhoff's ET1100/ET1200 or Microchip's LAN9252. The problem is that these dedicated chips add cost and complexity even at the earliest stages of development. Validating EtherCAT slave behavior still requires an ASIC-based circuit first. `ESP32S3_W5500_SOES` bypasses this assumption entirely in software. By combining the ESP32-S3, WIZnet W5500, and the SOES stack, it emulates the full EtherCAT slave controller functionality without any dedicated ESC hardware. --- ## 2. Components ![](https://maker.wiznet.io/upload/ckeditor5/648896702%5F1775141412%2Epng) ** The photo above shows a commercial ESP32-S3 development board with W5500 already integrated on-board, along with a 1.77" LCD (ST7735S), TF card slot, 8MB PSRAM, 16MB Flash, and CH340K USB-UART. This kind of all-in-one board means you can get started without wiring up separate modules. ### Hardware | Component | Role | | --- | --- | | ESP32-S3 | Main MCU. Handles EtherCAT frame parsing and ESC register emulation | | **WIZnet W5500** | SPI Ethernet controller. Receives raw EtherType 0x88A4 frames at the MAC level | | GPIO (DIN1~3) | 3-channel digital input (pull-up) | | GPIO (DOUT1~3) | 3-channel digital output | | UART1 | I/O status exchange interface with external devices | ### Pin Assignment | Function | GPIO | | --- | --- | | W5500 MOSI | 11 | | W5500 MISO | 13 | | W5500 CLK | 12 | | W5500 CS | 10 | | W5500 INT | 14 | | W5500 RST | 15 | | UART1 TX | 17 | | UART1 RX | 18 | | DIN1~3 | 1, 2, 4 | | DOUT1~3 | 5, 6, 7 | --- ## 3. The Role of W5500 In this project, the W5500 is more than just an Ethernet interface — it is the **physical entry point for all EtherCAT communication**. EtherCAT frames do not use TCP/IP. They are transmitted directly as raw Ethernet frames identified by EtherType 0x88A4. The W5500 receives these raw frames at the MAC level and passes them to the ESP32-S3 over SPI, completely bypassing any conventional network stack. | Role | Details | | --- | --- | | **Raw Frame Reception** | Receives EtherCAT frames (EtherType 0x88A4) at the MAC level | | **SPI Interface** | Connected to ESP32-S3 via SPI; built-in hardware TCP/IP stack minimizes MCU overhead | | **Response Frame Transmission** | Sends processed EtherCAT responses from ESP32-S3 back to the master | W5500 was chosen because its characteristics match this architecture well: SPI-based connectivity that works with any MCU, support for raw packet transmission and reception, and a stable, widely available supply chain. --- ## 4. How It Works The full processing flow of the system is as follows: ```plaintext EtherCAT Master (TwinCAT 3) │ EtherType 0x88A4 raw frame ▼ W5500 (SPI Ethernet) │ Passes raw frame via SPI ▼ ESP32-S3 ├─ EtherCAT datagram parsing │ (APRD / APWR / FPRD / FPWR / BRD / BWR / LRW) ├─ ESC register space emulation (16KB RAM) ├─ FMMU logical-to-physical address mapping ├─ EEPROM (SII) emulation └─ SOES stack integration ├─ EtherCAT state machine handling ├─ CoE (CANopen over EtherCAT) └─ PDO I/O ├─ TxPDO: DIN1~3 → sent to master └─ RxPDO: DOUT1~3 ← received from master ``` ### EtherCAT Object Configuration | Index | Name | Direction | | --- | --- | --- | | 0x6000:01~03 | DIN1, DIN2, DIN3 | TxPDO (Slave → Master) | | 0x7000:01~03 | DOUT1, DOUT2, DOUT3 | RxPDO (Master → Slave) | ### TwinCAT Integration The repository includes an ESI XML file (`ESP32S3_SOES.xml`). Copy it to TwinCAT's device description directory, reload device descriptions, and the device will appear as "ESP32S3_SOES_W5500" during a scan. No manual configuration required. ### UART1 Interface The UART1 interface (115200 8N1) allows external devices to simulate digital input states or monitor output status. - Send `1` / `2` / `3` → Toggle DIN1~3 - When TwinCAT changes DOUT values → Receive `DO:xyz` format --- ## 5. Tech Stack Summary | Category | Details | | --- | --- | | **Main MCU** | ESP32-S3 | | **Ethernet Chip** | WIZnet W5500 (SPI, hardware TCP/IP stack built-in) | | **EtherCAT Stack** | SOES (Simple Open EtherCAT Slave, GPLv2) | | **Build System** | ESP-IDF v5.3.x, CMake | | **ESC Implementation** | Software emulation (no dedicated ASIC required) | | **Supported Datagrams** | APRD, APWR, FPRD, FPWR, BRD, BWR, LRW | | **CoE Support** | Yes (CANopen over EtherCAT) | | **Compatible EtherCAT Masters** | TwinCAT 3 and standard EtherCAT masters | | **I/O Configuration** | 3x DI, 3x DO + UART1 | | **Language** | C (97%), CMake (3%) | | **License** | SOES: GPLv2 / Application code: as-is | --- ## 6. Expandability This implementation provides a working EtherCAT slave environment using only an ESP32-S3 and W5500. The ability to validate EtherCAT slave behavior without a dedicated ESC ASIC makes it a practical reference structure for the early stages of developing industrial IoT devices or compact I/O modules. PDO mappings and CoE objects in the SOES stack can be extended to fit specific project requirements, and the W5500 + MCU combination is straightforward to port to a custom PCB. The minimal part count and stable supply chain also make it well-suited for repeated application across designs. --- ## FAQ **Q. Does it actually communicate with TwinCAT 3 without a dedicated EtherCAT slave chip?** Yes. The repository includes the ESI XML file, and per the README, the device is recognized after a device scan in TwinCAT 3. **Q. Can W5500 be replaced with a different Ethernet chip?** The current codebase is built around W5500's raw packet reception capabilities. Porting to another chip that supports raw frame handling is possible, but would require modifications at the driver level. **Q. Can this architecture be used in a real product?** Software ESC emulation has inherent limitations in real-time performance compared to dedicated ASICs. That said, it is a practical structure for prototyping, education, and non-real-time I/O control applications. --- > **GitHub**: > > --- Source: https://maker.wiznet.io/Grace_Koo/projects/esp32s3-w5500-soes/