FPGA Based Multichannel Bit Error Rate Tester for Spacecraft Data Acquisition System

Its a research paper , in this paper for this project they have used WIZnet 5300 (Ethernet Controller) and it is used for communication between FPGA and PC with an application
ORIGINAL POST
By Manoj Kumar A, Department of Electronics and Instrumentation Engineering, Karunya University,
components
Hardware Components
w5300
X 1
wiznet chip
Altera Stratix II
X 1
FPGA
details

ucc_fpga.PNG 2015-08-25-12.32.16-1024x576 2015-08-25-12.32.16-1024x576 2015-08-25 12.34.12 2015-08-25 12.32.59 2015-08-25 12.32.45 2015-08-25 12.32.35 2015-08-25 12.32.24 2015-08-25 12.32.16

Original Link:  https://www.researchgate.net/publication/332577041_FPGA_based_Multichannel_Bit_Error_Rate_Tester_for_Spacecraft_Data_Acquisition_System

Its a research paper , in this paper for this project they have used WIZnet 5300 (Ethernet Controller) and it is used for communication between FPGA and PC with an application.

 

Bit Error Rate (BER) is a principle measure of data transmission link performance. BER tester (BERT) consists of a Pattern Generator and an Analyzer that can be set to the same pattern. The payload data transmitted from the spacecraft consists of one, two or three channels per carrier based on the modulation scheme. The traditional equipments can do BER analysis for only one channel at a time. In order to support multichannel BER analysis, a Personal Computer (PC) based system is designed and implemented in Altera Stratix II (EP2S130F1508C5N) FPGA. Ethernet is configured using WIZnet 5300 (Ethernet Controller) and it is used for communication between FPGA and PC with an application. Application is used to transmit the Pattern Generator’s configurations from PC to FPGA and to receive Analyzer’s status. Packet processing is done for this communication using User Datagram protocol (UDP). On the whole, traditional equipments are replaced by the designed and implemented bit error rate tester.

For generator, the inputs are from the PC with application. For three channels namely CH1, CH2 and CH3, the various input configuration parameters are clock, reset, PN selection (PN7, PN15, PN17, PN20 and PN23), error rate injection and manual error. The output of generator is clock and the PRBS data. The outputs are available in the LVDS O/P interface. For analyzer, the inputs are clock and PRBS data of the three channels. The outputs are clock presence, BER lock, PN detected, no of bits elapsed during lock, no of bits elapsed during unlock for each channel.The PCI-X card consists of Altera Stratix II (EP2S130F1508C5N) FPGA, WIZnet 5300 (Ethernet Controller), LAN Port, LVDS I/O interfaces. A PC with a GUI is connected to the PCI-X Card through LAN port. The block diagram is shown in figure

WIZnet 5300 (Ethernet Controller)

In this Ethernet controller memory is extended to 128Kbyte and 16 bit bus interface is supported. It

consists of eight hardware sockets which can be used simultaneously. In this project only one is used.

Communication can be established using Protocols such as Transmission Control Protocol (TCP), User

Datagram Protocol (UDP), IPRAW and MACRAW. TCP is a connection-oriented protocol. UDP is a

connection-less protocol. UDP supports unicast, broadcast and multicast methods. In this project UDP

(unicast method) is used [6]. Socket status transition for UDP (Unicast method) and UDP operation flow are

shown in figure 5 and 6 respectively.

Direct addressing mode is implemented. For 16bit data bus width, ADDR [9:1] is used and ADDR0

is connected to ground or floated. ‘BIT16EN’ is internally pulled-up, so it is no problem if it is allowed to

float. The connections are shown in figure

 

 

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